Micron (and the broader DRAM industry) moved away from literal nanometer labels toward alphanumeric designations once feature sizes entered the teens of nanometers. The half-pitch of the active area in the memory cell array serves as the primary reference metric. The 10 nm-class spans roughly 10–19 nm half-pitch. Micron’s sequence begins with 1x (first generation), followed by 1y (second), 1z (third), then Greek-letter nodes: 1α (1-alpha, fourth), 1β (1-beta, fifth), and 1γ (1-gamma, sixth).

Position in Micron’s DRAM Roadmap and Approximate Feature Scale

Around 2020, Micron described the early 10 nm-class progression as follows:

• 1Xnm: approximately 19–17 nm (earlier, less dense production).
• 1Ynm: approximately 16–14 nm (mainstream bit production at that time).
• 1Znm: approximately 13–11 nm.
• Subsequent nodes (1α and beyond) continued scaling, with density gains accelerating at 1α.

Independent analyses place the 1y design rule near 17 nm. Micron’s 1y products reached volume production in the late 2010s (with detailed floorplan and process reports appearing around 2019). By the early 2020s it had become a high-volume mainstream node before yielding ground to 1z and later generations.

The 1y node sits in the era of pure deep-ultraviolet (DUV) multi-patterning. Micron delayed extreme-ultraviolet (EUV) lithography until the 1γ node (its sixth-generation 10 nm-class process), relying instead on sophisticated multi-patterning techniques with 193 nm immersion lithography for critical layers.

Cell Architecture and Process Characteristics

DRAM cells at this generation continued to use the industry-standard 6F² layout (one access transistor plus one capacitor). Key traits of Micron’s 1y implementation include:

• Active-area emphasis: Micron shifted emphasis so that active-area pitch became the smallest critical dimension (a change that began at 1x and continued). This aligned Micron more closely with Samsung and SK hynix practices.
• Word-line and bit-line pitches: Scaled alongside active features, though not always at identical rates.
• Capacitor and dielectric evolution: High-k dielectric materials and capacitor integration (cylindrical or evolving toward quasi-cylindrical forms) were optimized. Later analyses note material and process refinements that began or continued through Micron’s D1y and D1z generations.
• Peripheral and isolation changes: Micron had already removed the isolation gate line in the cell design starting from the D1x generation; this simplification carried forward.
• Lithography: Heavy reliance on multi-patterning (self-aligned double patterning and related techniques) to achieve sub-wavelength features. No EUV was employed.

These choices improved packing density while managing electrical parameters such as leakage, retention, and sensing margins—persistent challenges as features shrink.

Density, Die Size, and Performance Gains

Relative to Micron’s preceding 1x node, the 1y generation delivered measurable density uplift:

• An 8 Gb DDR4 die on 1y achieved approximately 0.205 Gb/mm² bit density—a roughly 22.7 % increase over the corresponding 1x DDR4 die.
• Cell size for Micron’s 1y measured about 0.0024 µm², very close to contemporary Samsung 1y cells (~0.0023 µm²). This closed much of the earlier density gap that had existed between the companies at the 1x generation.

Bit-density growth slowed across the 1x → 1y → 1z transitions compared with earlier historical nodes. Micron later accelerated the pace at 1α, reporting ~40 % density improvement versus 1z (partly from process scaling and partly from design efficiency). The 1y node nevertheless provided meaningful cost-per-bit reduction through higher bits per wafer and supported mainstream DDR4 and LPDDR4/LPDDR4X products of its era.

Power and performance benefits were incremental rather than revolutionary: smaller transistors and optimized circuits improved energy efficiency and supported higher data rates available in the contemporaneous JEDEC standards, but the dramatic power reductions and speed jumps seen in later nodes (e.g., 15–20 % power cuts or multi-gigabit-per-second leaps at 1β and 1γ) were not yet characteristic of 1y.

Manufacturing Context and Competitive Landscape

Micron produced 1y DRAM in its existing high-volume fabs (primarily in Taiwan and Japan at the time). Yield ramp and cost control were critical, as multi-patterning increases process complexity and cycle time. By the time 1z reached meaningful volume (around 15 % of Micron’s DRAM bit production in late 2020), 1y remained an important workhorse node.

Competitively, Samsung and SK hynix pursued parallel 1y nodes with similar cell sizes. TechInsights comparisons of early DDR5 devices later showed residual use of 1y-class cells by some vendors even as Micron moved ahead on 1z for certain products, illustrating staggered adoption across the industry.

Challenges and the Path Beyond 1y

Scaling at 1y already encountered the physical limits of optical lithography and the increasing difficulty of maintaining capacitor capacitance, sense-amplifier margins, and reliability (including emerging concerns such as row-hammer susceptibility). Shrink factors (the ratio of successive design rules) remained relatively aggressive for Micron through much of this period but began to rise (become less aggressive) at later nodes, signaling the approaching limits of conventional 6F² planar scaling.

The 1y node therefore represents a transitional milestone: it demonstrated that multi-patterning DUV could still deliver competitive density and cost improvements inside the 10 nm-class window, while highlighting the need for the computational lithography, further multi-patterning refinement, high-k metal-gate CMOS enhancements, and eventual EUV introduction that defined 1α, 1β, and especially 1γ.

Summary Table of Early 10 nm-Class Nodes (Approximate)

Node	Approx. Half-Pitch / Design Rule	Generation in 10 nm Class	Key Notes (Micron Context)	Lithography
1x	~19–17 nm	1st	Larger cell relative to peers; design change	DUV multi-patterning
1y	~16–14 nm / ~17 nm DR	2nd	~0.205 Gb/mm² (8 Gb DDR4 example); cell ~0.0024 µm²	DUV multi-patterning
1z	~13–11 nm	3rd	Further density gains; still DUV	DUV multi-patterning
1α	Sub-15 nm cell	4th	~40 % density vs. 1z; high bit density	Advanced DUV
1β / 1γ	Further shrink	5th / 6th	HKMG refinements; EUV begins at 1γ	DUV → EUV hybrid

(Values are approximate and drawn from contemporaneous industry reporting and reverse-engineering analyses; actual measured pitches vary by layer and vendor.)

In historical perspective, Micron’s 1y node successfully extended cost-effective DRAM scaling at a time when many observers questioned how far conventional planar cells could go. It delivered tangible density and manufacturing advantages that supported the high-volume memory market of the late 2010s and early 2020s, while setting the stage for the more aggressive process and design innovations that followed. As the industry continues to confront the physical limits of 6F² cells and explores vertical or alternative architectures, the engineering solutions pioneered or refined at the 1y generation remain foundational to understanding modern DRAM process technology.

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1) Cell Architecture and Process Characteristics of Micron’s 1y DRAM Node

Fundamental Cell Architecture: 6F² Design

Micron’s 1y DRAM retained the industry-standard 6F² cell layout, consisting of one access transistor and one storage capacitor per bit. This geometry had been the mainstream choice since the mid-2000s and remained dominant through the early 10 nm-class nodes.

• The cell area is defined as approximately 6 × F², where F represents the minimum feature size (closely tied to the active-area half-pitch).
• Reported cell size for Micron 1y products is approximately 0.0024 µm².
• This was very close to contemporary Samsung 1y cells (~0.0023 µm²), marking a significant closing of the earlier density gap that existed at the 1x node.

Micron introduced a redesigned cell architecture at the 1x generation and carried it forward into 1y. A notable change was the removal of the isolation gate line in the cell array (implemented starting at D1x). This simplification reduced process complexity while maintaining adequate isolation between adjacent active regions.

Access Transistor: Buried Channel Array Transistor (BCAT) with Saddle-Fin Active

The access transistor uses a buried channel array transistor (BCAT) structure combined with a saddle-type (bulky) fin active region—often described as a saddle-fin or bulky fin-type active.

Key features include:

• Buried metal wordline (b-WL): The wordline is recessed into the silicon, forming a recessed channel. This improves short-channel control and reduces the cell’s footprint compared with planar or elevated-gate approaches.
• Saddle-fin (bulky fin) active: The silicon active region is shaped into a saddle or trapezoidal fin profile. This increases effective channel width and length, improving on-current while suppressing leakage and short-channel effects.
• Island-type staggered active patterns: Active regions are formed as discrete islands in a staggered layout rather than continuous stripes. This supports higher packing density and better isolation.
• Active pitch is the smallest critical dimension among the three primary pitches (active, wordline, and bitline). This prioritization aligned Micron’s approach more closely with Samsung and SK hynix practices.

Compared with Micron’s earlier 2y-class designs, the 1x/1y redesign reduced active pitch substantially (approximately 40 % in the 1x transition) while adjusting wordline and bitline pitches to balance electrical performance and manufacturability.

Storage Capacitor: Honeycomb Cylindrical Structure

The storage element is a cylindrical capacitor arranged in a honeycomb (hexagonal) packing pattern for maximum density within the available cell area.

• Capacitor-on-Bitline (COB) configuration: The capacitor is stacked above the bitline.
• Storage node landing pad (SNLP) and plug: These connect the capacitor bottom electrode to the access transistor drain/source region.
• High-k dielectric: Micron optimized high-k dielectric materials and thickness at the D1y (and subsequent D1z) generations. Typical materials in this era included ZrO₂- and Al₂O₃-based stacks (often multilayer). Dielectric thickness was progressively reduced in later nodes (reaching ~6–7 nm by D1z) to maintain capacitance as lateral dimensions shrank.
• Capacitance targets remained in the low-to-mid teens of femtofarads per cell, sufficient for reliable sensing given the process generation’s sense-amplifier design.

While pure cylindrical capacitors were still standard at 1y, the industry (including later Micron nodes) began transitioning toward quasi-cylindrical forms to improve mechanical stability and capacitance density as aspect ratios increased.

Bitline and Supporting Structures

• Straight line-type bitlines: Bitlines run in continuous straight lines rather than complex zigzag patterns.
• Air-gap spacers: Bitline air-gap spacers were employed to reduce parasitic capacitance between adjacent bitlines, improving signal integrity and power efficiency.
• Bitline pitch was reduced relative to prior generations (approximately 13 % in the 1x transition), though it remained larger than the active pitch.

Process Integration and Lithography Characteristics

The 1y node relied entirely on deep-ultraviolet (DUV) immersion lithography (193 nm ArF) with advanced multi-patterning techniques. Extreme ultraviolet (EUV) lithography was not used; Micron deferred EUV introduction until the much later 1γ node.

Critical layers (active, wordline, bitline, and storage-node contacts) employed multi-patterning schemes such as self-aligned double patterning (SADP) or related litho-etch sequences to achieve the required pitches. Overlay accuracy, etch profile control, and film stress management were essential to maintaining yield at these dimensions.

Additional process elements common to the generation included:

• Advanced shallow trench isolation (STI) tailored to the island-type active layout.
• Optimized doping profiles and work-function engineering for the buried wordline gate to control threshold voltage and leakage.
• Multi-layer metallization in the periphery and array edge, with tungsten and copper interconnects.

Summary of Key Architectural Traits

Feature	Micron 1y Characteristic	Purpose / Benefit
Cell layout	6F²	Standard density / manufacturability balance
Active structure	Saddle-fin (bulky fin), island-type staggered	Higher drive current, better isolation
Wordline	Buried metal (b-WL) with recess channel (BCAT)	Reduced footprint, improved SCE control
Capacitor	Honeycomb cylindrical, COB, high-k dielectric	Capacitance density within scaled cell
Isolation	No isolation gate line (from D1x onward)	Process simplification
Primary pitch priority	Active pitch smallest	Aligns with industry density leaders
Lithography	DUV multi-patterning only	Cost-effective scaling without EUV

These architectural and process choices allowed Micron’s 1y node to deliver roughly 23 % higher bit density on representative 8 Gb DDR4 dies compared with its own 1x products, while supporting reliable operation in DDR4 and LPDDR4/LPDDR4X applications of the late 2010s. The design represented a mature evolution of the 6F² planar cell rather than a radical departure, setting the foundation for the more aggressive scaling, high-k metal-gate refinements, and eventual EUV adoption that characterized later Micron nodes.

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2) Density, Die Size, and Performance Gains

This section examines how Micron’s second-generation 10 nm-class (1y / D1y) process translated cell scaling and design refinements into higher bits per square millimeter, smaller dies for a given capacity, and the performance envelope of commercial products. Publicly available reverse-engineering data (primarily TechInsights analyses of 8 Gb DDR4 parts) provide the most concrete numbers; manufacturers rarely publish exact die dimensions or wafer-level bit counts.

Bit Density Improvement Versus Prior Nodes

The clearest published comparison is for 8 Gb DDR4:

• Micron 1y 8 Gb DDR4: approximately 0.205 Gb/mm²
• Micron 1x 8 Gb DDR4: approximately 0.137 Gb/mm²
• Resulting density gain: ~22.7 % versus Micron’s own 1x generation.

Cell size moved from a larger 1x value to about 0.0024 µm² on 1y, nearly matching Samsung’s contemporary 1y cell (~0.0023 µm²). This closed most of the density gap that had existed at 1x, when Micron’s cell was notably larger than Samsung’s.

Samsung’s 1y LPDDR4X 8 Gb die reached a higher 0.237 Gb/mm², illustrating that peripheral efficiency and exact pitch choices still produced vendor-to-vendor differences even when cell sizes were similar.

Density scaling from 1x → 1y (and then 1y → 1z) was slower than the later jump Micron achieved at 1α (~40 % versus 1z). The 1y generation therefore represented solid but incremental progress rather than a step-function leap.

Die Size Implications

Using the 0.205 Gb/mm² figure, an 8 Gb (1 GB) 1y DDR4 die occupies roughly 39 mm². A contemporaneous TechInsights floorplan reference for a Micron 17 nm-class 1y 8 Gb part lists dimensions of approximately 8.57 mm × 4.64 mm (~39.8 mm²), consistent with that calculation.

By comparison:

• Micron 1x 8 Gb DDR4 die: 58.48 mm²
• Shrink from 1x to 1y on the same 8 Gb DDR4 capacity: on the order of 30+ % smaller die area.

Smaller dies increase the number of good chips per 300 mm wafer (after edge exclusion and yield), which is the primary lever for lowering cost per bit. Micron also offered a “1xs” shrink variant of the 1x node that optimized periphery (write drivers, column decoders) while keeping the same array design rule; 1y combined both array scaling and continued peripheral efficiency work.

Performance Characteristics of 1y Products

Representative 1y silicon (e.g., MT40A2G4SA-062E family) supported standard high-volume DDR4 speeds of the period:

• Data rate: DDR4-3200 (1600 MHz clock, 3200 MT/s)
• I/O voltage: 1.2 V
• Typical CAS latency: CL22 on the 3200 bin
• Organization examples: 2G × 4, 8 Gb monolithic die

These were not exotic “record-breaker” speeds; they aligned with JEDEC DDR4-3200 and the mainstream server/client market of 2018–2020. The process node’s contribution was enabling reliable, high-yield production of these speeds at higher density and lower cost per bit rather than a large leap in raw frequency or a dramatic power cut.

Power improvements were incremental—smaller transistors and refined circuits reduced energy per bit relative to 1x, but the large percentage reductions advertised on later nodes (1β and 1γ) were not characteristic of 1y. The node supported both DDR4 (computing) and LPDDR4/LPDDR4X (mobile) product lines.

Context Within the Broader Scaling Trend

Generation	Example 8 Gb DDR4 Bit Density	Approx. Cell Size	Notes
Micron 1x	0.137 Gb/mm²	Larger than peers	Design-rule change already underway
Micron 1y	0.205 Gb/mm²	~0.0024 µm²	+22.7 % vs own 1x; closed gap to Samsung
Samsung 1y LPDDR4X	0.237 Gb/mm²	~0.0023 µm²	Higher peripheral efficiency in that product
Later Micron 1α (8 Gb DDR4)	0.315 Gb/mm²	1,672 nm²	Much larger subsequent jump

In short, the 1y node delivered a commercially important density and die-size improvement that made high-volume 8 Gb DDR4 and corresponding LPDDR parts more cost-effective. It was a mature, production-proven step on the 10 nm-class roadmap rather than the most aggressive scaling Micron later achieved.

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3) Manufacturing Context and Competitive Landscape

This section places Micron’s second-generation 10 nm-class (1y / 1Y / D1y) DRAM process in its production and market setting: where the wafers were made, how the node was ramped, how it compared with Samsung and SK hynix, and what that meant during the late-2010s DRAM cycle.

Where 1y Was Manufactured

Micron’s DRAM front-end at the time was concentrated in two regions:

• Hiroshima, Japan (Micron Memory Japan, former Elpida). This site served as both a development and early-volume center. The 1Y process was already being ramped there in 2018. Completion of the B2 building in mid-2019 enabled higher-volume 1Y output, with LPDDR4-class products as an early focus. The same site then moved on to 1Z later that year. Process learning from Hiroshima was transferred to Taiwan for scale.
• Taiwan (primarily Taichung and related sites, including capacity inherited from Rexchip). Taiwan accounted for the majority of Micron’s DRAM wafer output. Large-volume 1y production followed the Japanese process transfer rather than originating as a purely Taiwan-first node.

No EUV tools were used. The node relied on 193 nm ArF immersion lithography plus multi-patterning. That kept capital intensity lower than later EUV-based nodes but increased process steps, cycle time, and overlay/etch-control demands.

The 1y node therefore sat in Micron’s classic Japan-develop / Taiwan-scale model that continued through 1α and 1β before EUV arrived at 1γ.

Production Timing and Role in the Mix

• Introduction and early volume: roughly 2018–2019.
• Mainstream bit contribution: 2019–2020, overlapping the start of 1Z ramp.
• Product mix: 8 Gb-class DDR4 (e.g., parts such as MT40A2G4SA-062E) and LPDDR4/LPDDR4X for mobile.

By late 2020 Micron was already shifting mix toward 1Z (reported at about 15 % of its DRAM bits in 3Q20) while 1y remained an important workhorse. The node did not stay at the leading edge for long; its commercial value was high-volume, cost-reduced 8 Gb DDR4 and low-power mobile DRAM during a period of intense price pressure.

Competitive Positioning Versus Samsung and SK Hynix

The DRAM industry was (and remains) a tight triopoly. Around 2018–2019 typical revenue shares were on the order of:

• Samsung: ~45 %
• SK hynix: ~29 %
• Micron: ~21 %

2019 was a down cycle: DRAM revenue fell sharply (industry DRAM revenue dropped on the order of 37 %) because of oversupply and collapsing ASPs. All three vendors saw large year-over-year revenue declines; technology leadership mattered for cost position, not for escaping the cycle.

On process:

• Samsung generally introduced each 10 nm-class generation first and often led on bit density in a given product type (e.g., 1y LPDDR4X at ~0.237 Gb/mm² versus Micron 1y DDR4 at ~0.205 Gb/mm²).
• Micron’s 1y cell size (~0.0024 µm²) nearly matched Samsung’s 1y cell (~0.0023 µm²), closing a gap that had been more visible at 1x. TechInsights later noted that the Samsung–Micron cell-size gap narrowed at D1y and that all three vendors converged on similar cell sizes by D1z.
• SK hynix followed a parallel 1y path with comparable 6F² architecture.

A revealing later snapshot is the first wave of 16 Gb DDR5 parts: Samsung and SK hynix still used 1y-class cells on some early DDR5, while Micron used a more advanced 1z cell and produced a smaller die. That illustrates staggered node adoption rather than lockstep leadership.

Strategic Implications

1y was not Micron’s most aggressive node, but it was commercially important:

• It delivered a real density and die-size step versus Micron’s own 1x parts, improving bits per wafer.
• It demonstrated that DUV multi-patterning could still support competitive 10 nm-class production without EUV.
• Hiroshima’s role as process incubator and Taiwan’s role as volume engine set the template Micron reused on subsequent nodes.
• In a three-player market, matching cell size and keeping cost competitive mattered more than being first by a quarter; 1y helped Micron stay in that race through the 2019 downturn and into the 1Z/1α transition.

The node’s manufacturing story is therefore one of disciplined process transfer, DUV-era cost control, and closing a historic density gap with the Korean vendors—not of lithography breakthroughs or market-share upheaval.

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4) Challenges and the Path Beyond Micron’s 1y DRAM Node

The 1y node proved that DUV multi-patterning could still deliver a commercial density step inside the 10 nm-class window. It also made the next set of limits obvious. This section covers the technical constraints that were already visible at 1y, why scaling slowed, and how Micron’s subsequent nodes (1z through 1γ) responded.

Process and Physical Limits Visible at 1y

Several constraints intensified rather than appeared for the first time at 1y:

• Lithography complexity. Features sat well below the 193 nm immersion wavelength. Multi-patterning (SADP and related sequences) delivered the required pitches, but each extra litho-etch cycle raised cost, cycle time, overlay risk, and defect opportunity. Micron’s strength in pitch multiplication let it postpone EUV until 1γ; the trade-off was growing process-step count.
• Capacitor aspect ratio and capacitance. Cell area shrinks with the square of feature size, while stored charge must stay large enough for a reliable sense-amplifier decision. Capacitors became taller, narrower holes with high-k liners only a few nanometers thick. Aspect ratios climbed far beyond everyday mechanical analogies; capacitance per cell continued a long-term decline that later nodes would have to offset with materials, geometry, and circuit tricks.
• Buried wordline integrity. Recessed metal wordlines under the active silicon are structurally and electrically stressed as pitch shrinks. Line-edge roughness, wiggling, and local thinning become yield and reliability issues. Later 10 nm-class work explicitly targeted wordline profile control and gate-oxide process changes to reduce breaks and improve refresh and row-hammer behavior.
• Sensing margin. Smaller capacitance plus bitline parasitics and sense-amplifier offset leave less voltage difference between “0” and “1.” Design mitigations (offset cancellation, on-die ECC, tighter refresh policies) became more important as cells scaled.

Reliability: Retention and Row Hammer

As wordline pitch falls, capacitive coupling and trap-assisted charge loss between neighboring cells increase. Row-hammer (and related disturb mechanisms) worsen with each shrink: the number of activations needed to flip an adjacent cell drops, and the problem is documented across all three major vendors’ chips from this era onward. Saddle-fin / BCAT structures that help drive current can also lower barriers that once limited disturb. Device-level fixes help but do not eliminate the need for architectural mitigations (targeted refresh, tracking, later on-die features).

Retention (variable retention time, random telegraph noise) likewise becomes harder as dielectric thickness and storage-node volume shrink. 1y-era parts still met product specs, but the margin for error was thinner than on 20 nm-class nodes.

Why Density Growth Slowed After 1x

Micron itself noted that bit-density gains decelerated across 1x → 1y → 1z, then accelerated again at 1α (about 40 % versus 1z, part process and part design efficiency). Shrink factors (successive design-rule ratios) that had been relatively aggressive for years began to rise toward 0.9+ by 1z, a sign that 6F² planar cells were getting harder to pack. Patterning, capacitor etch, and electrical margins all contributed. The 1y node sits in the middle of that slowdown: useful, but no longer a “free” doubling of bits per wafer.

Micron’s Path After 1y

Node	Role relative to 1y	Key responses to 1y-era limits
1z	Immediate successor	Further DUV multi-patterning; continued cell and periphery shrink; still no EUV at Micron
1α	Density reset	Computational lithography + multi-patterning; ~40 % density vs 1z; first sub-15 nm-class cell at Micron
1β	Last major DUV node	2nd-gen HKMG CMOS, higher LPDDR5X speeds, ~35 % density vs 1α
1γ	First Micron EUV DRAM	EUV + DUV hybrid, next-gen HKMG, redesigned BEOL; ~30 % bits/wafer and ~20 % power vs 1β

Micron’s strategy was explicit: extract as much as possible from multi-patterning and design efficiency, then introduce EUV when the extra masks and cycle time of DUV outweighed scanner cost. Competitors adopted EUV earlier (Samsung from 1z-class products, SK hynix on 1a-class). Micron accepted a later EUV start in exchange for cost control on 1y–1β.

Materials and integration also evolved: high-k stacks were optimized through D1y/D1z; capacitors moved toward quasi-cylindrical forms at some vendors; HKMG in the periphery improved transistor performance and area at 1β/1γ.

Longer Horizon Beyond Planar 6F²

Industry analyses treat ~10 nm-class 6F² as approaching a practical ceiling. Extending planar DRAM further requires work-function engineering, still-thinner high-k, better sensing, row-hammer hardening, and eventually high-NA EUV. Beyond that, vendors are developing vertical or 3D DRAM concepts (stacked cells, vertical channel transistors, hybrid bonding) because lateral F scaling alone cannot restore historical density doubling.

1y did not invent these problems, but it was the generation at which they became the central planning constraint rather than background risk. The node’s value was proving that a second 10 nm-class shrink was still manufacturable at scale. Everything after 1y—tighter shrinks, HK

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