Micron’s 1x DRAM node marked the company’s entry into the 10 nm-class era of memory manufacturing. It was the first-generation process in that class (typically corresponding to a half-pitch in the 17–19 nm range), succeeding earlier 20 nm-class nodes such as 2y nm and enabling smaller dies, higher bit density, and improved cost-per-bit for DDR4 and LPDDR4 products. This node laid the foundation for subsequent generations (1y, 1z, 1α, 1β, and 1γ) while highlighting both the opportunities and growing difficulties of DRAM scaling.
The 10 nm-class naming convention itself reflects industry realities: exact nanometer figures became less useful as feature sizes approached physical limits, so manufacturers adopted 1x/1y/1z (and later Greek-letter) labels tied to half-pitch of the active area in the memory cell array.
Historical Context and Timeline of the 10 nm-Class Transition
DRAM scaling followed Moore’s Law-like shrinks for decades, moving from hundreds of nanometers down through 20 nm-class processes. By the mid-2010s the industry faced increasing challenges in lithography, capacitor aspect ratios, and cell-to-cell interference.
- Samsung began volume production of 1x nm DRAM (estimated ~18 nm) in 2017 for DDR4, LPDDR4, and LPDDR4X.
- Micron followed with its own 1x nm products, analyzed in detail by TechInsights in 2018. These appeared in DDR4 DIMMs and LPDDR4 devices (for example in certain Huawei Mate 10 phones).
- Micron’s 1x node sat between its prior 2y nm (~20 nm-class) generation and the later 1y (roughly 14–16 nm) and 1z (11–13 nm) nodes.
- Volume production of 1z 16 Gb DDR4 began in 2019; 1α (fourth-generation 10 nm-class) shipping started in 2021.
The 1x node therefore represented Micron’s first serious step into the 10 nm-class window that would dominate DRAM manufacturing for years.
Technical Architecture of Micron’s 1x Node
Micron retained the industry-standard 6F² cell design. Key process and structural features identified in teardown analyses included:
- Saddle-type bulky-fin active areas (a FinFET-like transistor structure) with island-type staggered active patterns.
- Buried metal wordlines featuring recessed channels.
- Straight-line bitlines.
- Honeycomb cylindrical cell capacitors.
Compared with Micron’s own 2y nm generation, the 1x node reduced active-area pitch by approximately 40 % and bitline pitch by 13 %, while wordline pitch increased by about 20 %. This pitch rebalancing meant the overall 6F² cell size did not shrink as aggressively as the active pitch alone might suggest. Micron’s 1x cell was reported as roughly 29 % larger than Samsung’s contemporaneous 1x cell.
Lithography remained deep-ultraviolet (ArF immersion) with multi-patterning; extreme ultraviolet (EUV) lithography would not appear in Micron DRAM until the much later 1γ node.
Typical measured die sizes for 8 Gb parts:
- DDR4: 58.48 mm²
- LPDDR4: 52.77 mm²
These represented die-size reductions of 18.3 % (DDR4) and 17.14 % (LPDDR4) versus equivalent-density 2y nm dies.
Density, Performance, and Cost Implications
Bit-density gains were modest on the DDR4 side but more pronounced on mobile parts:
| Product | Die Size (8 Gb) | Bit Density | Change vs. Prior 2y nm Generation |
|---|---|---|---|
| DDR4 | 58.48 mm² | 0.137 Gb/mm² | +11.4 % |
| LPDDR4 | 52.77 mm² | 0.152 Gb/mm² | ~+60 % |
Samsung’s 1x parts achieved higher bit density (~0.189 Gb/mm²) thanks to a smaller cell. Micron therefore traded some density for its particular process choices (active-pitch priority and specific capacitor/transistor integration). The net result was still a meaningful improvement in bits per wafer and lower cost per gigabit relative to the previous generation, supporting broader adoption of 8 Gb and higher-density DDR4/LPDDR4.
Power and performance benefits were incremental rather than revolutionary; later nodes (especially 1α onward) delivered more dramatic 15–40 % density and efficiency jumps.
Comparison with Contemporaries and Scaling Challenges
Samsung led the 1x introduction and maintained a density advantage at that generation. SK Hynix followed a similar 6F², buried-wordline path. All three major DRAM makers encountered the same physics: capacitor height-to-width aspect ratios became extreme, leakage and sensing margins tightened, and conventional lithography struggled with the smallest features.
Micron’s 1x implementation already showed the industry pattern of selective pitch scaling rather than uniform shrinks. Subsequent generations continued this trend, with shrink factors approaching 0.9 and beyond, making each new node harder and more expensive.
Evolution Beyond 1x and Lasting Relevance
The 1x node was quickly succeeded:
- 1y and 1z delivered further (though slowing) density gains.
- 1α (2021) produced a reported 40 % bit-density increase over 1z through a combination of process shrinks and design-efficiency improvements, still using multi-patterned DUV rather than EUV.
- 1β and 1γ (the latter introducing EUV plus next-generation high-k metal-gate CMOS) continued the progression into the mid-2020s.
By 2026 the leading-edge nodes are 1γ and beyond, yet 1x (and 1y) technology remains in use at certain Micron facilities for long-lifecycle products serving automotive, industrial, defense, medical, and networking markets. These applications value stability, qualification longevity, and supply security over the absolute latest density. Micron’s Manassas, Virginia, fab, for example, previously ran 1x/1y processes before beginning the transition to 1α for DDR4 and LPDDR4.
The 1x node therefore occupies a dual role: a historical milestone that opened the 10 nm-class chapter for Micron, and a still-relevant process for specialized, high-reliability memory that does not require the newest lithography or the highest bit density.
In short, Micron’s first-generation 10 nm-class DRAM process demonstrated that continued scaling was possible even as conventional photolithography approached its limits. It delivered measurable density and cost improvements while exposing the engineering trade-offs that would define the next decade of DRAM development. Later nodes built directly on the architectural and process lessons of 1x, confirming its place as the starting point of Micron’s modern 10 nm-class roadmap.
1) Historical Context and Timeline of the 10 nm-Class Transition
The 10 nm-class transition in DRAM manufacturing marked a pivotal shift from the 20 nm-class era, driven by the need for higher bit density, lower power, and cost reduction as traditional scaling hit physical and economic limits. This period, spanning roughly 2016 to the early 2020s, saw the three major DRAM producers—Samsung, SK Hynix, and Micron—adopt a new naming convention (1x, 1y, 1z, later extending to Greek letters) because exact nanometer measurements no longer captured the half-pitch of the active area in the cell array. Micron’s 1x node was its first-generation entry into this class, arriving shortly after Samsung’s industry-first move and setting the stage for subsequent shrinks.
The transition was not a single leap but a series of incremental, increasingly difficult nodes. Each generation delivered smaller cell sizes (typically 6F² design), tighter pitches, and more bits per wafer, but shrink factors slowed as capacitor aspect ratios grew extreme and lithography (primarily ArF immersion multi-patterning) approached its limits. EUV lithography would not become practical for DRAM until later generations.
Pre-Transition Context: The 20 nm-Class Foundation (circa 2014–2016)
Before the 10 nm-class, DRAM makers operated in the 20 nm-class (often labeled 2x, 2y, or 2z). Samsung commercialized 20 nm 4 Gb DDR3 in 2014 and followed with 20 nm-class LPDDR4 and DDR4 products. These nodes already used advanced techniques such as buried wordlines, high-k dielectrics, and multi-patterning. Bit density gains were still healthy, but the industry recognized that further uniform shrinks would become uneconomical without new patterning strategies or materials. The 10 nm-class was defined as half-pitches in the 10–19 nm range, starting with 1x (typically 17–19 nm).
Industry Timeline of the 10 nm-Class Rollout
The following table summarizes key mass-production and development milestones for the first three generations of the 10 nm-class, focusing on announced volume production of leading products (primarily 8 Gb or 16 Gb DDR4/LPDDR4). Dates reflect official announcements or confirmed teardowns.
| Year / Period | Samsung | Micron | SK Hynix (approximate) | Notes |
|---|---|---|---|---|
| 2016 (Q1–Q2) | First 10 nm-class (1x) 8 Gb DDR4 mass production (April) | — | Development ongoing | Samsung industry first; >30% wafer productivity gain vs. 20 nm. Used ArF immersion + quadruple patterning. |
| 2017 | 1y (2nd-gen 10 nm-class) 8 Gb DDR4 mass production (December) | 1x products appearing in market (late 2017–early 2018) | 1x ramp | Samsung 1y delivered ~30% productivity gain over its own 1x. Micron 1x teardowns confirmed in 2018 DIMMs and mobile devices. |
| 2018 | Continued 1y ramp; LPDDR4X volume | 1x volume production established; 1y development and early ramp (Hiroshima fab) | 1y introduction | Micron 1x die sizes: ~58.5 mm² (8 Gb DDR4), ~52.8 mm² (LPDDR4). Bit-density gains modest vs. Samsung. |
| 2019 (H1–H2) | 1z development announced (March); 1z 8 Gb DDR4 mass production later in year | 1z 16 Gb DDR4 volume production (August)—industry first for this density/node combo | 1z development | Micron emphasized 40% power reduction vs. prior 8 Gb parts and higher bit density vs. its 1y. |
| 2020–2021 | 1z volume; 1a (4th-gen) development | 1z ~15% of bit production (Q3 2020); 1α volume shipments begin (January 2021) | 1z/1a progression | Density gains slowed between 1x–1z; 1α delivered a sharper ~40% bit-density jump for Micron. |
Samsung consistently led the introduction of each new generation by 12–18 months in the early phase. Micron closed the gap on 1z and then led on certain 16 Gb products and later nodes. SK Hynix followed a similar cadence, often matching or trailing Samsung slightly.
Micron-Specific Path Through the Transition
Micron entered the 10 nm-class later than Samsung but executed a rapid catch-up:
- 1x (first-generation 10 nm-class, ~17–19 nm half-pitch): Products reached the market by early 2018. TechInsights analysis of DDR4 DIMMs and LPDDR4 in consumer devices confirmed the node’s 6F² cell with saddle-fin transistors, buried recessed-channel wordlines, and honeycomb capacitors. Die shrinks versus Micron’s prior 2y nm generation were 17–18%, with bit-density improvements of 11% (DDR4) to ~60% (LPDDR4).
- 1y (second-generation): Ramped in 2018–2019, notably at the expanded Hiroshima facility (B2 building completed mid-2019 for higher 1y volume).
- 1z (third-generation): Volume production of 16 Gb DDR4 started August 2019. This node represented Micron’s first claim of industry leadership on a specific high-density product within the 10 nm-class.
The company’s internal roadmap at the time treated 1x as the entry point, with each subsequent letter representing a further (but diminishing) shrink. By late 2020 Micron publicly extended the roadmap to 1α, 1β, 1γ, and 1δ, noting that bit-density growth had slowed across 1x-to-1z before accelerating again at 1α through a mix of process and design optimizations.
Broader Industry Dynamics and Challenges During the Transition
Several factors shaped the 10 nm-class rollout:
- Lithography constraints: All early 10 nm-class nodes relied on 193 nm ArF immersion lithography plus multi-patterning (double, triple, or quadruple). EUV was evaluated but deemed not cost-effective until the mid-2020s (Micron’s 1γ).
- Cell-design trade-offs: Makers prioritized different pitches (active vs. wordline vs. bitline). Micron’s 1x, for example, shrank the active pitch aggressively while relaxing the wordline pitch, resulting in a cell that was larger than Samsung’s contemporaneous 1x cell.
- Economic reality: Each new node required heavier capital investment and longer yield ramps. The industry therefore stretched the 10 nm-class across four or more generations rather than jumping immediately to a “true” sub-10 nm process.
- Product mix: Early 10 nm-class output focused on DDR4 for servers/PCs and LPDDR4/LPDDR4X for mobile. Higher-density 16 Gb parts became the vehicle for later nodes (1z and beyond).
By 2021 the first three generations (1x–1z) were mature, and the industry had moved into the fourth-generation 10 nm-class (1α / 1a). The original 1x node, while no longer leading-edge, continued in production at some sites for long-lifecycle industrial, automotive, and defense applications that prioritize qualification stability over maximum density.
The 10 nm-class transition therefore succeeded in extending DRAM scaling for nearly a decade, delivering successive waves of higher-capacity, more efficient memory even as the underlying physics grew more unforgiving. Micron’s 1x node was the company’s opening move in that era—an essential, if not the earliest, step that enabled everything that followed.
2) Technical Architecture of Micron’s 1x Node
Micron’s 1x DRAM node employed a conventional 6F² one-transistor, one-capacitor (1T1C) cell while introducing targeted changes in active-area patterning, pitch allocation, and transistor geometry to enter the 10 nm-class. These architectural choices balanced density gains against the practical limits of 193 nm ArF immersion lithography and capacitor scaling. The result was a functional first-generation 10 nm-class process that delivered measurable die-size and bit-density improvements over Micron’s prior 2y nm generation, even if the overall cell did not shrink as aggressively as some contemporaries.
The design reflected industry consensus at the time: buried wordlines, fin-style access transistors, and stacked cylindrical capacitors remained the workhorse combination. Micron’s implementation, however, showed a noticeable shift in how it allocated the three critical pitches (active, wordline, and bitline).
Cell Layout and 6F² Design
Micron retained the 6F² cell that it had pioneered years earlier and that had become the industry standard. In this layout the unit cell occupies an area of approximately 6 times the square of the minimum feature size F (typically defined by half-pitch). The cell is rectangular, with the bitline running in one direction and the wordline in the perpendicular direction.
- Active areas form isolated “islands” arranged in a staggered pattern rather than continuous lines.
- An isolation (dummy) wordline is no longer required in the same way as some earlier Micron generations; the staggered island layout plus shallow-trench isolation provides separation.
- The capacitor sits above the bitline (capacitor-over-bitline, or COB, configuration), allowing the storage node to occupy the remaining vertical space.
This 6F² arrangement was already mature by the 1x generation. The novelty lay in how the pitches were scaled relative to one another.
Access Transistor and Wordline Architecture
The access transistor uses a saddle-type bulky-fin (also called FinET or saddle-fin) structure. The silicon active region is formed into a three-dimensional fin that increases effective channel width without enlarging the cell footprint. The wordline is a buried metal gate that wraps around the recessed channel of this fin.
Key characteristics:
- Recessed-channel access transistor (similar to BCAT concepts used across the industry) to control short-channel effects and leakage at the smaller dimensions.
- Buried metal wordline (typically a TiN/W or comparable stack) sitting below the silicon surface, reducing parasitic capacitance and allowing a more compact layout.
- Island-type staggered active patterning that differs from the more linear or dash-line actives seen on Micron’s earlier 2y nm parts.
Compared with Micron’s own 2y nm generation, the 1x node reduced the active-area pitch by approximately 40 percent. This was the most aggressive pitch shrink and aligned Micron’s approach with Samsung and SK Hynix, who had already made the active pitch the smallest of the three critical dimensions.
Bitline and Capacitor Structures
Bitlines are straight-line metal features running perpendicular to the wordlines. Their pitch was reduced by only about 13 percent versus the 2y nm node—less aggressive than the active-pitch shrink.
The storage capacitor is a honeycomb-style cylindrical stacked capacitor. The “honeycomb” description refers to the dense packing of the cylindrical storage nodes, which maximizes capacitance per unit area while maintaining mechanical stability. High-k dielectric films (typically zirconium-oxide-based stacks common in that era) line the cylinders to achieve the required capacitance (tens of femtofarads) despite the shrinking footprint.
Wordline pitch actually increased by roughly 20 percent relative to the 2y nm generation. This rebalancing meant the overall 6F² cell area did not shrink in proportion to the active-pitch reduction. TechInsights analysis concluded that Micron’s 1x cell was approximately 29 percent larger than Samsung’s contemporaneous 1x cell.
Pitch Comparison and Resulting Cell Size
The table below summarizes the directional pitch changes from Micron’s preceding 2y nm node to 1x, based on teardown measurements.
| Dimension | Change vs. 2y nm | Relative Priority in 1x Node | Implication |
|---|---|---|---|
| Active-area pitch | –40 % | Smallest of the three | Aligns with Samsung/SK Hynix strategy; enables denser transistor packing |
| Bitline pitch | –13 % | Intermediate | Moderate density gain |
| Wordline pitch | +20 % | Relaxed | Trades some density for process window and electrical performance |
| Overall 6F² cell | Little or no net shrink | — | Cell larger than Samsung 1x equivalent |
Die-level outcomes for 8 Gb parts illustrate the net effect:
- DDR4 die: 58.48 mm² (18.3 % smaller than equivalent 2y nm die)
- LPDDR4 die: 52.77 mm² (17.14 % smaller)
- Resulting bit densities: 0.137 Gb/mm² (DDR4, +11.4 %) and 0.152 Gb/mm² (LPDDR4, ~+60 %)
The larger relative gain on the LPDDR4 part suggests additional array-efficiency or peripheral-circuit optimizations on the mobile product.
Lithography and Process Integration
All critical layers used 193 nm argon-fluoride (ArF) immersion lithography with multi-patterning (double or quadruple patterning depending on the layer). Extreme-ultraviolet (EUV) lithography was not employed; it would appear only years later on Micron’s 1γ node. Overlay control, spacer-defined patterning, and precise etch processes were therefore essential to print the staggered island actives and the tall, high-aspect-ratio capacitor cylinders.
Typical supporting process elements of the era included:
- Shallow-trench isolation (STI) for active-area definition
- High-k metal-gate (or metal-gate) stacks for the buried wordline
- Air-gap or low-k spacers around bitlines in some implementations to reduce parasitic capacitance
- Multiple metal layers in the periphery with copper or tungsten interconnects
These choices kept capital intensity manageable while still delivering a first-generation 10 nm-class node.
The 1x architecture therefore represents a pragmatic engineering compromise: it adopted the industry’s preferred active-pitch priority and 3-D fin transistor while accepting a less aggressive overall cell shrink. The resulting chips were smaller and denser than Micron’s previous generation and commercially viable, even if they lagged Samsung’s 1x density. Subsequent nodes (1y onward) would continue refining the same 6F², buried-wordline, cylindrical-capacitor foundation until physical limits forced more radical changes such as EUV and, eventually, 4F² or 3-D DRAM concepts.
3) Density, Performance, and Cost Implications
Micron’s 1x DRAM node delivered measurable but uneven gains in bit density, modest performance improvements, and a corresponding reduction in cost per bit through higher wafer productivity. The benefits were more pronounced on mobile LPDDR4 parts than on standard DDR4, reflecting differences in array efficiency and product optimization. While the node did not match Samsung’s contemporaneous 1x density leadership, it still represented a commercially important step that lowered the cost of 8 Gb devices and supported the industry’s shift toward higher-capacity modules.
These implications must be viewed in context: 1x was an entry-level 10 nm-class process. Later nodes (1z, 1α, 1β, 1γ) produced larger percentage jumps in density and power efficiency. The 1x generation’s value lay in establishing the process platform and delivering the first wave of 10 nm-class cost reduction.
Bit-Density Improvements
TechInsights measurements of 8 Gb parts provide the clearest picture:
| Product | Die Size | Bit Density | Change vs. Micron 2y nm | Comparison with Samsung 1x |
|---|---|---|---|---|
| DDR4 | 58.48 mm² | 0.137 Gb/mm² | +11.4 % | Samsung ~0.189 Gb/mm² (higher) |
| LPDDR4 | 52.77 mm² | 0.152 Gb/mm² | ~+60 % | Samsung ~0.189 Gb/mm² (Micron ~20 % lower) |
The larger relative gain on LPDDR4 suggests additional design work on array efficiency or peripheral circuitry for the mobile product. The DDR4 improvement was more modest because Micron’s 1x cell itself did not shrink much versus its own 2y nm predecessor (the 6F² cell area stayed roughly comparable after pitch rebalancing). Samsung’s tighter cell gave it a density advantage at this generation.
On a 300 mm wafer (usable area approximately 63,800 mm² after edge exclusion), the smaller dies translate into more chips per wafer. A theoretical calculation for the 8 Gb DDR4 part yields roughly 1,090 potential dies before yield and street losses—noticeably more than the prior, larger 2y nm die. At typical mature yields this produces a meaningful increase in gigabits (or terabytes) of DRAM output per wafer start.
Performance Characteristics
Public data on 1x-specific speed bins and power consumption versus the immediate prior generation is limited; manufacturers typically highlighted larger jumps starting with the 1z node. Expected benefits of the shrink include:
- Faster transistor switching from the smaller, fin-style access devices.
- Potential for modestly lower operating voltage or reduced leakage due to the buried-wordline and recessed-channel architecture.
- Incremental bandwidth improvements consistent with DDR4/LPDDR4 standards of the period (typically 2400–3200 MT/s for DDR4 and comparable LPDDR4 rates).
Later Micron nodes advertised explicit figures (for example, ~40 % power reduction on 1z 16 Gb parts versus older 8 Gb devices, 15–20 % power savings plus 40 % density on 1α). The 1x node itself delivered the foundational process improvements that made those subsequent gains possible rather than headline-grabbing performance leaps of its own.
Cost-per-Bit and Manufacturing Economics
DRAM cost is dominated by bits per wafer. The 1x node improved this metric through two mechanisms:
- Smaller die size (17–18 % reduction for 8 Gb parts) increases the number of candidate chips per wafer.
- Higher bit density (especially the 60 % jump on LPDDR4) multiplies the output of each chip.
The net result is more saleable gigabits per wafer start, which lowers the cost per bit once yields stabilize. This is the classic DRAM scaling economic model: each successful node shrink amortizes the high fixed costs of a 300 mm fab across more bits.
Additional cost considerations at the 1x generation included:
- Continued use of existing 193 nm ArF immersion lithography and multi-patterning rather than the far more expensive EUV tools that arrived years later.
- Process complexity from staggered island actives and high-aspect-ratio capacitors, which can affect yield during the ramp.
- Competitive positioning: Micron’s lower density versus Samsung at 1x meant slightly higher cost per bit on equivalent products until later nodes closed the gap.
In practice the 1x node enabled Micron to participate in the 8 Gb DDR4 and LPDDR4 market at competitive (if not leading) cost points and to begin the multi-year process of converting its installed base of 20 nm-class capacity.
Broader Implications and Limitations
The density and cost gains were sufficient to justify the node but revealed the slowing pace of traditional 6F² scaling. Subsequent generations required more aggressive pitch shrinks, design-efficiency improvements, and eventually EUV plus new CMOS technologies to restore larger percentage advances. The 1x architecture therefore served as both a commercial success and a warning that future cost reductions would demand greater innovation than simple linear shrinks.
By delivering higher wafer output and lower cost per bit on high-volume 8 Gb products, Micron’s first 10 nm-class node helped sustain the DRAM industry’s long-term price-per-bit decline even as physical limits tightened. Those economics, more than raw performance numbers, defined the node’s practical value.
4) Comparison with Contemporaries and Scaling Challenges
Micron’s 1x DRAM node entered a competitive 10 nm-class landscape already occupied by Samsung and closely followed by SK Hynix, revealing both the shared architectural consensus of the era and the growing physical and economic difficulties of continued 6F² scaling. Samsung held a clear density lead at this generation, while Micron’s implementation traded some cell-area efficiency for process-window and electrical considerations. All three companies faced the same tightening constraints: lithography complexity, capacitor scaling limits, and diminishing returns on pitch shrinks.
The 1x generation therefore illustrated both the industry’s ability to keep DRAM viable and the reasons why later nodes would require more radical process changes.
Head-to-Head Comparison at the 1x Generation
The table below summarizes key metrics from TechInsights teardowns and contemporary analyses of 8 Gb-class parts. Samsung’s 1x products (mass-produced from 2016) set the benchmark; Micron’s 1x parts reached the market in 2017–2018.
| Metric | Micron 1x | Samsung 1x | SK Hynix 1x (approx.) | Notes |
|---|---|---|---|---|
| Typical bit density | 0.137 Gb/mm² (DDR4) 0.152 Gb/mm² (LPDDR4) | ~0.189 Gb/mm² (DDR4 & LPDDR4X) | Similar to Samsung range | Samsung ~20–38 % higher density |
| 8 Gb die size | 58.48 mm² (DDR4) 52.77 mm² (LPDDR4) | Smaller than Micron | Comparable to Samsung | Micron dies 17–18 % smaller than its own 2y nm but larger than Samsung 1x |
| Cell size vs. Samsung | ~29 % larger | Reference | Close to Samsung | Result of Micron’s pitch rebalancing |
| Active pitch priority | Smallest of three pitches | Smallest of three pitches | Smallest of three pitches | Industry alignment at 1x |
| Wordline / bitline | WL pitch relaxed (+20 % vs. Micron 2y) | Tighter overall | Tighter | Micron accepted larger cell for process margin |
| Lithography | 193 nm ArF immersion + multi-patterning | Same | Same | No EUV at this generation |
| Cell architecture | 6F², saddle-fin, buried recessed-channel WL, honeycomb cylindrical capacitor | 6F², similar 3-D transistor & stacked capacitor | 6F², buried WL, cylindrical capacitor | Broad industry consensus |
Samsung’s tighter pitches and more aggressive cell shrink produced both higher bit density and better wafer productivity at 1x. Micron’s larger cell and relaxed wordline pitch reflected a more conservative integration strategy that prioritized yield and electrical stability during its first 10 nm-class ramp. SK Hynix occupied a middle position, generally tracking Samsung’s density more closely than Micron’s.
By the next generation (1y), Micron had narrowed the cell-size gap, and by 1z it achieved leadership on certain 16 Gb products. The 1x comparison therefore captures a snapshot of Micron still in catch-up mode.
Shared Architectural Approach
Despite density differences, the three companies converged on the same core cell:
- 6F² layout with staggered or island-type active areas.
- Buried metal wordline wrapping a recessed-channel (saddle-fin or similar) access transistor.
- Stacked cylindrical (or honeycomb) capacitors using high-k dielectrics.
- Capacitor-over-bitline (COB) configuration.
This consensus had been building since the 20 nm-class and 30 nm-class nodes. The 1x generation simply refined it rather than inventing a new cell type. Differences appeared mainly in pitch allocation, exact fin geometry, capacitor aspect ratio, and peripheral-circuit efficiency.
Scaling Challenges That Intensified at 1x
The 10 nm-class transition exposed several compounding difficulties that would only grow in subsequent nodes:
Lithography and patterning complexity
193 nm ArF immersion plus multi-patterning (double or quadruple) was already near its practical limit for the smallest features. Overlay errors, spacer uniformity, and defectivity increased cost and cycle time. EUV was not yet economical for DRAM; Micron and others continued multi-patterning until the mid-2020s.
Capacitor scaling
Cylindrical capacitors required ever-higher aspect ratios to maintain capacitance (typically 20–30 fF) as the footprint shrank. Mechanical stability, leakage through the high-k dielectric, and uniform deposition inside deep holes became critical yield limiters. Honeycomb packing helped density but added process steps.
Pitch-rebalancing trade-offs
Micron’s decision to shrink the active pitch 40 % while relaxing the wordline pitch 20 % illustrates the problem: not every dimension can be scaled equally without hurting transistor performance, isolation, or lithography window. The net 6F² cell therefore improved less than a uniform shrink would suggest.
Transistor and leakage control
Shorter channels and closer cell-to-cell spacing increased short-channel effects, subthreshold leakage, and emerging reliability issues such as row-hammer. Buried-wordline and fin-style transistors mitigated these effects but added process complexity.
Economic and yield realities
Each new node demanded more masks, more process steps, and longer yield ramps. Shrink factors (actual cell-area reduction versus the previous node) were already declining; they would later approach 0.9, meaning almost no area benefit from the next letter in the 1x–1y–1z sequence. Capital intensity rose while the bits-per-wafer gain per node shrank.
These challenges explain why the industry stretched the “10 nm-class” across four or more generations instead of jumping to a true sub-10 nm process and why later nodes introduced EUV, new high-k metal-gate CMOS, and ultimately exploration of 4F² or 3-D DRAM architectures.
Strategic Implications
Samsung’s early 1x lead gave it a temporary cost and time-to-market advantage in high-volume DDR4 and LPDDR4. Micron’s 1x node, while not density-leading, still delivered enough die-size and bit-density improvement over its own 2y nm parts to remain competitive and to fund the next shrinks. The comparison underscores that DRAM leadership at this stage was measured in quarters of ramp speed and a few percent of cell area rather than revolutionary architectural differences.
The scaling difficulties visible at 1x foreshadowed the slower, more expensive progress that followed. Micron’s subsequent nodes closed the density gap and eventually led in selected products, but they did so by solving the same set of problems—lithography, capacitor integrity, and pitch optimization—at ever-smaller dimensions. The 1x generation therefore served as both a competitive snapshot and a preview of the engineering constraints that would define DRAM development for the rest of the decade.
5) Evolution Beyond 1x and Lasting Relevance
Micron’s 1x DRAM node served as the foundational first-generation 10 nm-class process that enabled a multi-year sequence of successive shrinks, each delivering incremental (and later more substantial) gains in density, power efficiency, and cost. While 1x itself was quickly superseded for leading-edge products, the architectural and process lessons it established—6F² cell, buried recessed-channel wordline, saddle-fin transistor, and multi-patterned 193 nm lithography—remained the platform for 1y, 1z, 1α, 1β, and the EUV-enabled 1γ node. At the same time, 1x (and 1y) technology retained commercial relevance for long-lifecycle applications that value stability and qualification longevity over maximum bit density.
The evolution illustrates both the persistence of the 10 nm-class paradigm and the eventual need for more disruptive changes.
Sequential Node Progression After 1x
Micron followed a roughly annual-to-18-month cadence of lettered nodes within the 10 nm-class:
- 1y (second-generation, ~14–16 nm half-pitch): Ramped in 2018–2019, notably at the expanded Hiroshima facility. Delivered further die-size reduction and bit-density improvement over 1x, closing some of the gap with Samsung.
- 1z (third-generation, ~11–13 nm): Volume production of 16 Gb DDR4 began in August 2019. Micron claimed industry-first status for this density on the node and advertised substantial power reductions (approximately 40 % versus older 8 Gb parts) plus higher bit density versus its own 1y generation.
- 1α / 1-alpha (fourth-generation): First shipments in January 2021. Produced a reported 40 % bit-density increase over 1z through a combination of process shrinks and array-efficiency design improvements (roughly 10 % of the gain attributed to design). Still used multi-patterned DUV rather than EUV. Cell size measured at 1,672 nm² on analyzed 8 Gb DDR4 parts.
- 1β / 1-beta (fifth-generation): Samples in 2022, volume production shortly thereafter (initially LPDDR5X). Delivered ~15 % power-efficiency and >35 % bit-density gains versus 1α.
- 1γ / 1-gamma (sixth-generation): Sampling and early production in 2025. First Micron DRAM node to incorporate EUV lithography (combined with DUV multi-patterning) plus next-generation high-k metal-gate CMOS. Achieved >30 % bits-per-wafer increase, 15 % higher speed (up to 9,200 MT/s on 16 Gb DDR5), and >20 % power reduction versus 1β.
Each step refined the same 6F² foundation established at 1x. Shrink factors gradually worsened (approaching 0.9 by later nodes), meaning the industry extracted less area benefit from each successive letter. Design-efficiency improvements and new materials therefore became as important as pure lithographic shrinks.
Lasting Production and Application Relevance of 1x Technology
Although leading-edge output moved to 1α and beyond by the early 2020s, 1x and 1y processes continued in volume at selected Micron facilities for products with long qualification cycles:
- Automotive, industrial, medical, networking, defense, and aerospace markets often require 7–10+ year supply commitments and extensive reliability qualification.
- These segments prioritize proven process stability, known failure modes, and second-source options over the newest density or speed.
- Micron’s Manassas, Virginia, fab, for example, ran 1x and 1y nodes for years before beginning the transition to 1α in 2026 specifically to serve these long-lifecycle DDR4 and LPDDR4 customers. The upgrade was projected to quadruple DDR4 wafer output at the site while keeping the same product families.
In this role the original 1x node (and its immediate successor) functions as a mature, high-yield “workhorse” process rather than a performance leader. The same pattern appears across the industry: older 10 nm-class nodes remain in production long after they cease to be leading-edge.
Broader Industry Trajectory and Why 1x Still Matters
The 1x node’s architectural choices—pitch rebalancing, fin-style transistor, and cylindrical capacitor—proved scalable enough to support four additional generations before EUV and new CMOS became necessary. This longevity validated Micron’s conservative first-generation approach even if it initially lagged Samsung in density.
At the same time, the slowing shrink factors visible after 1x confirmed that traditional 6F² planar DRAM was approaching its practical limit. Later industry efforts therefore include:
- Greater use of EUV and high-NA EUV.
- Exploration of 4F² cells and vertical-channel transistors.
- 3-D DRAM stacking concepts for nodes beyond the current 10 nm-class.
Micron’s 1x process therefore occupies a dual historical position: it was the company’s entry ticket into the 10 nm-class era that defined DRAM manufacturing from the late 2010s through the mid-2020s, and it remains a production workhorse for applications that do not require the newest lithography or the highest bit density. Its technical DNA is still visible in every subsequent Micron DRAM node, while its continued use in specialized markets demonstrates that not every product needs to be on the leading-edge process.