SK Hynix’s 1a(1α/1-Alpha) DRAM Node: The company’s fourth-Generation 10 nm-Class process Technology

SK Hynix’s 1a DRAM node represents the company’s fourth-generation 10 nm-class process technology, marking a pivotal step in DRAM scaling through EUV lithography adoption, higher wafer productivity, and improved power efficiency. This node, often written as 1anm or D1a, followed the 1x, 1y, and 1z generations and enabled SK Hynix to expand high-density products such as LPDDR4 and later DDR5 while competing with Samsung and Micron.

The “10 nm-class” label in DRAM refers to successive shrinks of the memory cell half-pitch (typically the active-area or wordline/bitline dimension) rather than a precise transistor gate length used in logic processes. Generations progressed as 1x (roughly 17–19 nm class), 1y, 1z, then 1a as the fourth. Exact feature sizes vary by vendor and measurement point; SK Hynix’s 1a is commonly described in the mid-14 nm range for key dimensions.

DRAM Node Naming and Scaling Context

DRAM makers use lettered generations because traditional nanometer labels became less meaningful as cells approached physical limits of planar 6F² (six times the minimum feature size squared) buried-channel-array-transistor (BCAT) architectures. Each step reduces cell area, raising bits per wafer, but shrink factors have slowed (often 0.9 or higher), making lithography, capacitor materials, and interconnects more critical.

SK Hynix reached 10 nm-class production in the late 2010s. The 1z node (third generation) delivered 16 Gb DDR4 with notable density and power gains without full EUV. The 1a node built on that foundation.

Production Start and First Products

SK Hynix announced mass production of 1a-node 8 Gb LPDDR4 mobile DRAM in July 2021. This was the company’s first full use of extreme ultraviolet (EUV) lithography in high-volume DRAM manufacturing after limited trials on 1y-node parts. All subsequent 1a production used EUV.

The node delivered an estimated 25 percent increase in chips per wafer versus the prior 1z generation, improving cost competitiveness amid rising DRAM demand. The initial LPDDR4 devices supported 4266 Mbps (the JEDEC maximum for that standard) with approximately 20 percent lower power consumption than predecessor products. Supply to smartphone makers began in the second half of 2021.

By late 2021 SK Hynix sampled 24 Gb DDR5 devices on the same 1a process—the industry’s highest single-die density at the time—enabling 48 GB and 96 GB modules. These parts used EUV and offered up to 33 percent higher speed plus 25 percent lower system-level power for equivalent module capacity compared with earlier 16 Gb 1y-node DDR5.

Later, 1a-node DDR5 received industry-first validation on Intel’s 4th-generation Xeon Scalable (Sapphire Rapids) processors.

SK hynix Starts Mass Production of 1anm DRAM Using EUV Equipment – SK hynix Newsroom

Official SK Hynix imagery of 1a-node packaged DRAM devices.

Technical Architecture and Innovations

TechInsights analyses of production 1a-node dies (for example, a 24 Gb DDR5 part) describe a stacked CMOS process with five back-end-of-line metal layers (one aluminum, three copper, one tungsten) plus an aluminum redistribution layer. Key features include:

Buried wordline forming the gate of the BCAT.
Bitline under the capacitors.
EUV used at metal-1 and the storage-node landing pad (SNLP) levels.
Measured pitches of approximately 39.5 nm (wordline) and 44.5 nm (bitline).

Compared with a 1z-node LPDDR5 example (wordline ~42 nm, bitline ~47.4 nm), the 1a shrink is modest but sufficient for density and efficiency gains when combined with process optimizations and EUV. SK Hynix applied EUV to only one critical layer on 1a, versus more layers at Samsung; this lower initial complexity aided yield ramp (reports cited ~95 percent early yields).

The architecture remained 6F² planar. Capacitor and interconnect improvements supported the required cell capacitance while shrinking the footprint.

Performance, Density, and Efficiency Gains

Wafer productivity: +25 percent chips versus 1z at equivalent density.
Power: ~20 percent reduction on LPDDR4; further improvements on DDR5 implementations.
Speed: Full LPDDR4 spec (4266 Mbps); later DDR5 parts reached higher effective rates with the same process.
Density: Enabled 24 Gb single-die DDR5, a significant step from 16 Gb predecessors.

These gains translated into better battery life in mobile devices, lower data-center power draw, and higher bits per square millimeter. Micron’s contemporaneous 1α (Greek-letter equivalent) node achieved even higher reported bit density on some early parts through multi-patterning without EUV, illustrating different vendor trade-offs.

Competitive Position

Samsung, SK Hynix, and Micron all reached fourth-generation 10 nm-class production around 2021. Samsung used more EUV layers on its 1a-equivalent node and slightly tighter reported line widths in some analyses. Micron relied longer on argon-fluoride immersion multi-patterning for 1α before adding EUV on later nodes. SK Hynix’s earlier full-EUV commitment on 1a positioned it well for subsequent generations.

By 2024–2025 the industry had moved to 1b (fifth generation) and 1c (sixth generation). SK Hynix was first to develop 1c-node 16 Gb DDR5, applying EUV to additional layers and delivering further speed and power improvements. The 1a node remains relevant as a high-volume, cost-effective platform even as leading-edge production shifts forward.

Broader Impact and Evolution

The 1a node helped SK Hynix increase supply during a period of strong mobile and early server DDR5 demand. It also advanced the company’s ESG goals through lower manufacturing energy and product power. Subsequent nodes (1b, 1c) built directly on 1a process learning, increasing EUV layer count (1a: 1 layer; 1b: ~4 layers; 1c: 5+ layers) and enabling higher-bandwidth products such as HBM variants and LPDDR6.

Looking further, SK Hynix and peers are evaluating 4F² vertical-gate transistors and 3D DRAM stacking for sub-10 nm-class scaling, as conventional 6F² planar cells approach limits. High-NA EUV tools, first installed by SK Hynix for production development in 2025, will support those future nodes.

The 1a generation therefore sits at an important midpoint: it proved high-volume EUV DRAM manufacturing, delivered measurable cost and efficiency benefits, and provided the process foundation for the 1b/1c era that now powers AI-centric memory.

SK Hynix continues to apply 1a-derived know-how across its portfolio while ramping more advanced nodes, underscoring how incremental lithography and cell-engineering advances still drive DRAM progress even as architectural shifts loom.

1) DRAM Node Naming and Scaling Context

DRAM process nodes use a lettered generation system (1x, 1y, 1z, 1a, 1b, 1c and beyond) rather than precise nanometer labels because the industry needed a way to track incremental shrinks inside a broad “10 nm-class” range while physical scaling became increasingly difficult. This convention emerged around 2016 as DRAM half-pitches entered the 10–19 nm window and traditional numeric names lost meaning. The system emphasizes generational progress in cell density, power, and performance more than an exact feature size.

Why DRAM Naming Diverged from Logic Nodes

Logic process nodes (TSMC 3 nm, Intel 18A, etc.) have long been marketing labels with only loose connection to any single transistor dimension. DRAM naming stayed closer to a physical metric for longer: the half-pitch of the active area (or sometimes the wordline) in the memory-cell array. Half-pitch is half the repeating distance between identical features.

Once DRAM reached the 20 nm class, further shrinks of 1–2 nm per generation no longer justified new numeric names. Vendors therefore adopted a sequential lettering scheme inside the umbrella “10 nm-class” (roughly 10–19 nm half-pitch). The first three generations were labeled 1x, 1y and 1z. After exhausting the Roman alphabet they continued with 1a (fourth generation), 1b, 1c, and so on. Micron switched to Greek letters (1α, 1β, 1γ) for the same generations to avoid confusion with logic nodes. SK Hynix and Samsung kept Latin letters. Thus 1c and 1γ refer to the same sixth-generation 10 nm-class technology.

Approximate Feature-Size Mapping

Published analyses and vendor comments give these typical ranges (exact measured pitches vary by vendor, product, and which dimension is cited):

Generation	Common Label	Approximate Half-Pitch / Design Rule	Typical Introduction
1st	1x	17–19 nm	~2016
2nd	1y	14–16 nm	~2018
3rd	1z	11–15 nm	~2019–2020
4th	1a / 1α	~13–14.5 nm	2021
5th	1b / 1β	~12–13 nm	2022–2023
6th	1c / 1γ	~11–12 nm	2024–2025
7th	1d / 1δ	approaching 10 nm	2026+ (ramping)

These figures are industry approximations; TechInsights measurements of wordline and bitline pitches on actual dies often sit a few nanometers higher than the “node name.” The 6F² cell layout (cell area ≈ 6 × F²) has been standard since the late 2000s. Because area scales with the square of the feature size, even a modest linear shrink still yields useful density gains.

Scaling Challenges That Drove the Naming Shift

DRAM cells consist of one access transistor plus one high-aspect-ratio capacitor. Lateral shrinks reduce capacitor volume, so manufacturers compensate by making the capacitor taller (aspect ratios now exceed 50:1 and approach 100:1). This creates severe etch, deposition, and mechanical-stress problems. At the same time, lithography must pattern ever-tighter active, wordline and bitline features. Shrink factors (new F divided by previous F) have risen from ~0.75–0.85 in earlier nodes to 0.90–0.92 or higher, meaning each generation delivers less relative density improvement.

EUV lithography was introduced first on selected critical layers (SK Hynix began full 1a production with EUV in 2021) to reduce multi-patterning complexity. Even with EUV, the industry views conventional 6F² planar cells as approaching a practical limit near 10 nm. Roadmaps therefore point to 4F² vertical-gate transistors and, later, true 3D-stacked DRAM for nodes below 10 nm.

Industry Practice and Marketing Reality

Vendors rarely publish exact half-pitch numbers in press releases; they speak of “fourth-generation 10 nm-class” or “1a-node.” This reduces marketing wars over 0.5 nm differences that take years to realize. Samsung briefly disclosed a 14 nm figure for its 1a node in 2021, but the lettered system remains the common language. The result is a clear generational sequence that customers, analysts and competing fabs can track without needing teardowns of every die.

In short, the 1x–1c naming scheme is a pragmatic industry convention born from the physics of capacitor scaling and lithography limits. It lets DRAM makers communicate progress inside a shrinking process window while they prepare architectural changes (4F² and 3D) that will define the next decade of memory technology.

2) Production Start and Products

SK Hynix began high-volume production of its 1a-node DRAM in July 2021, starting with 8 Gb LPDDR4 mobile devices and rapidly expanding the process to higher-density DDR5 products. This marked the company’s first full-scale use of EUV lithography in DRAM manufacturing and delivered immediate gains in wafer output and power efficiency. The node subsequently supported a range of server, mobile, and early AI-memory applications before later generations took over leading-edge volume.

Official Production Start

On July 12, 2021, SK Hynix announced that mass production of 1a-node 8 Gb LPDDR4 DRAM had started that month. The company had previously qualified EUV on a limited basis during 1y-node manufacturing; 1a was the first node to use the technology across the entire production flow. All 1a wafers thereafter employed EUV at critical layers (primarily metal-1 and the storage-node landing pad).

The process yielded an estimated 25 percent more chips per 300 mm wafer compared with the preceding 1z node. Early yield reports cited figures around 95 percent, helping SK Hynix ramp output quickly during a period of strong mobile DRAM demand. Smartphone makers began receiving the new parts in the second half of 2021.

First Product: 8 Gb LPDDR4

The inaugural 1a device was an 8 Gb LPDDR4 chip targeting mobile platforms. Key specifications included:

Data rate: 4266 Mbps (the JEDEC maximum for LPDDR4)
Power reduction: approximately 20 percent versus prior-generation LPDDR4
Package options: standard mobile form factors for smartphones and thin laptops

This product improved both battery life and thermal headroom in flagship phones while lowering SK Hynix’s manufacturing cost per bit. The company explicitly linked the power savings to its ESG targets through reduced energy use in both fabrication and end-device operation.

Rapid Expansion to High-Density DDR5

By December 2021 SK Hynix shipped samples of a 24 Gb DDR5 die fabricated on the same 1a process—the highest single-die density then available. Compared with its earlier 16 Gb 1y-node DDR5, the 24 Gb part offered:

Up to 33 percent higher operating speed
25 percent lower system-level power for equivalent module capacity
Improved manufacturing efficiency that also reduced energy consumption during wafer processing

Initial modules were 48 GB and 96 GB configurations aimed at cloud data centers, AI/ML servers, and high-performance computing. The 24 Gb 1a die later appeared in consumer modules such as G.Skill Trident Z5 kits, confirming volume availability. TechInsights analysis of one such 24 Gb part confirmed EUV usage and measured wordline/bitline pitches of 39.5 nm / 44.5 nm.

SK Hynix also obtained industry-first validation of 1a-node DDR5 on Intel’s 4th-generation Xeon Scalable (Sapphire Rapids) processors in early 2023, accelerating adoption in enterprise servers.

Broader Product Portfolio on 1a

Although later nodes (1b and 1c) assumed leading-edge volume, the 1a process continued to support multiple product families:

Additional LPDDR4/LPDDR4X variants for mobile and PC
Standard-density 16 Gb DDR5 for both server RDIMM/LRDIMM and client UDIMM
Early CXL memory modules that combined 24 Gb 1a dies with the new interconnect
Base dies for some HBM stacks (the 1a node served as a mature, high-yield platform while 1b/1c ramped for HBM3E and HBM4)

The node’s combination of proven yield, EUV experience, and density made it a workhorse process even after more advanced nodes entered production. SK Hynix later converted portions of 1a capacity to newer nodes as demand shifted toward higher-bandwidth and higher-density parts.

The 1a production start therefore served two purposes: it immediately increased mobile DRAM supply and cost competitiveness, and it provided a stable, EUV-enabled foundation that SK Hynix used to launch higher-value DDR5 and server products within months. This dual-track approach helped the company capture share during the 2021–2023 memory cycle while preparing the process learning needed for subsequent 1b and 1c generations.

3) Technical Architecture and Innovations

SK Hynix’s 1a DRAM node introduced a refined 6F² buried-channel-array-transistor (BCAT) architecture combined with the company’s first high-volume use of extreme-ultraviolet (EUV) lithography. The process delivered measurable density and efficiency gains through tighter pitches, optimized interconnects, and targeted EUV insertion rather than a complete architectural overhaul. Independent teardowns of production 24 Gb DDR5 dies provide the most detailed public view of the implementation.

Core Cell and Transistor Structure

The 1a node retained the industry-standard 6F² cell layout that has been used since the late 2000s. Each bit consists of one access transistor and one high-aspect-ratio capacitor. The access transistor is a buried-channel-array transistor (BCAT) whose gate is formed by a buried wordline. This configuration keeps the transistor channel below the silicon surface, reducing leakage and improving reliability as feature sizes shrink.

Bitlines run beneath the capacitors, a layout that has become common in advanced DRAM to minimize parasitic capacitance and allow taller capacitor structures. The resulting cell pitches measured on a 24 Gb 1a DDR5 die were approximately 39.5 nm (wordline) and 44.5 nm (bitline). These represent a modest but consistent shrink from the preceding 1z-node pitches (roughly 42 nm / 47.4 nm on comparable LPDDR5 parts).

Interconnect and Back-End-of-Line Stack

The 1a process uses a five-layer BEOL metal stack plus an aluminum redistribution layer (RDL):

One tungsten layer
Three copper layers
One aluminum layer
Aluminum RDL on top

Vias are filled with tungsten (via-1 and via-4) or copper (via-2 and via-3). This relatively lean metal stack helped control cost and parasitic resistance while still supporting the higher current densities of DDR5. Later 1b-node parts added a sixth metal layer, showing the evolutionary nature of the interconnect scheme.

EUV Lithography Insertion

The most visible process innovation was the first full-volume application of EUV. SK Hynix had tested EUV on selected 1y-node layers; on 1a it deployed the technology at two critical levels—metal-1 and the storage-node landing pad (SNLP). Using EUV at these layers reduced the number of multi-patterning steps that would otherwise have been required with 193 nm argon-fluoride immersion lithography. The company stated that this approach improved both pattern fidelity and overall wafer productivity (the oft-cited 25 percent increase in chips per wafer versus 1z).

Subsequent nodes increased the number of EUV layers (four on 1b, five or more on 1c), confirming that 1a served as the learning vehicle for broader EUV adoption.

Capacitor and Materials Refinements

Although SK Hynix did not publicly detail every material change, the 1a generation continued the industry trend of high-k dielectric stacks and refined capacitor profiles to maintain the required ~6–7 fF cell capacitance despite the smaller footprint. TechInsights notes that capacitor integration had already shifted toward quasi-cylindrical shapes in the 1y/1z timeframe; 1a built on those process modules with tighter overlay control enabled by EUV at the SNLP. Gate materials remained titanium-nitride / polysilicon, consistent with contemporaneous Samsung and Micron 10 nm-class parts.

Design and Yield Optimizations

Beyond lithography, SK Hynix applied circuit-density and sensing-margin improvements that later became standard on 1b and 1c. These included higher peripheral-circuit packing and enhanced sense-amplifier designs to offset the increased resistance that accompanies smaller features. The combination of modest geometric shrink plus these design tweaks produced the observed 20 percent power reduction on LPDDR4 and the subsequent speed/power gains on 24 Gb DDR5. Early production yields near 95 percent indicated that the process window was sufficiently robust for rapid ramp.

In summary, the 1a node’s technical contribution was evolutionary rather than revolutionary: it refined an established 6F² BCAT platform, inserted EUV at the highest-value layers, and tightened interconnect and capacitor modules just enough to deliver a 25 percent productivity step and meaningful power/performance benefits. Those incremental advances supplied the process knowledge SK Hynix later leveraged for the more aggressive 1b and 1c generations.

4) Performance, Density, and Efficiency Gains

SK Hynix’s 1a DRAM node delivered measurable gains in three areas that matter most to memory customers: more bits per wafer, higher operating speeds within existing standards, and lower power consumption both at the chip and system level. These improvements stemmed from the combination of a modest cell shrink, EUV-enabled patterning accuracy, and circuit optimizations rather than a radical change in cell architecture. The results appeared first in mobile LPDDR4 and then more dramatically in high-density DDR5 products.

Wafer-Level Density and Productivity

The most frequently cited figure is a 25 percent increase in the number of DRAM chips produced from a 300 mm wafer compared with the preceding 1z node. This productivity step came from two sources:

A smaller cell footprint that allowed more dies to fit on the same wafer area.
Higher patterning fidelity from EUV at metal-1 and the storage-node landing pad, which reduced defect-related yield loss.

The 25 percent gain translated directly into lower cost per bit and greater supply elasticity during the 2021–2022 demand surge. For the later 24 Gb DDR5 die, the same process enabled the industry’s highest single-chip density at the time, moving from 16 Gb (typical on 1y-node DDR5) to 24 Gb without a proportional increase in die size.

Speed and Bandwidth

On the first 1a product—an 8 Gb LPDDR4 device—SK Hynix achieved the full JEDEC-specified 4266 Mbps data rate. This was the maximum the LPDDR4 standard allowed, so the node’s contribution was reliability at that speed rather than a new peak.

The more significant speed improvement appeared with 24 Gb DDR5 parts fabricated on the same process. SK Hynix reported up to 33 percent higher operating speed versus its earlier 16 Gb 1y-node DDR5. The combination of tighter pitches, improved sense-amplifier design, and lower interconnect resistance allowed the higher-density die to run at elevated frequencies while remaining within JEDEC DDR5 timing windows. These parts later appeared in both server RDIMMs and consumer modules.

Power Efficiency

Power reductions were consistent across product types:

LPDDR4: approximately 20 percent lower consumption than the previous generation at equivalent performance.
24 Gb DDR5: 25 percent lower system-level power when supporting the same module capacity (for example, comparing a 96 GB module built with 24 Gb 1a dies versus one built with 16 Gb 1y dies).

The savings originated from several process and design changes: reduced leakage in the BCAT transistor, lower parasitic capacitance from the bitline-under-capacitor layout, and more efficient peripheral circuitry made possible by the tighter design rules. SK Hynix also noted that the higher wafer productivity itself reduced energy consumed per bit during manufacturing, aligning the node with the company’s ESG goals.

Combined Impact on End Products

Taken together, the density, speed, and power improvements produced three practical outcomes:

Mobile devices gained longer battery life and cooler operation at the highest LPDDR4 speeds.
Servers and workstations could deploy higher-capacity DIMMs (48 GB and 96 GB modules) with better performance-per-watt.
Overall bit cost declined, helping SK Hynix compete on both price and specification during a tight supply period.

These gains were incremental rather than revolutionary, yet they were large enough to justify the capital investment in EUV tools and to serve as the process foundation for the subsequent 1b and 1c nodes, which built on the same architecture with additional EUV layers and further circuit refinements.

5) Competitive Position

SK Hynix entered fourth-generation 10 nm-class DRAM production in mid-2021 alongside Samsung and Micron, but pursued a distinct strategy that emphasized early, full-volume EUV adoption and high initial yields rather than maximum EUV layer count or the absolute smallest cell size. The 1a node therefore occupied a middle position: later to volume than Micron’s 1α on some products, more conservative on EUV layers than Samsung, yet competitive on cost, power, and time-to-market for both mobile and server applications.

Timeline and Volume Ramp

Micron announced volume shipments of 1α-node DRAM in January 2021 and began shipping parts that year. SK Hynix started 1a mass production in July 2021 with 8 Gb LPDDR4 and followed quickly with 24 Gb DDR5 samples in December 2021. Samsung’s equivalent 1a-class node also reached production in 2021. SK Hynix’s later start was offset by reports of higher early yields (approximately 95 percent versus Micron’s reported 70–80 percent at initial 1α ramp). This allowed SK Hynix to convert capacity rapidly once the process was qualified.

Lithography Approach

The three vendors chose different paths through the same process window:

SK Hynix: First company to use EUV for full high-volume DRAM production on the 1a node, applying it to one critical layer (later expanded). The approach reduced multi-patterning complexity while keeping capital intensity manageable.
Samsung: Deployed EUV on more layers (industry reports cited five layers on its 1a-equivalent node) and achieved slightly tighter reported line widths (approximately 14 nm versus SK Hynix’s 14–14.5 nm range).
Micron: Relied on advanced 193 nm argon-fluoride immersion multi-patterning for its 1α node and delayed EUV until later generations (1γ). This avoided the high cost of EUV tools in the near term but required more process steps.

SK Hynix’s single-layer EUV strategy proved sufficient to deliver the advertised 25 percent wafer-productivity gain and gave the company early operational experience that it later scaled to four-plus layers on 1b and 1c.

Density, Power, and Performance Claims

Micron published the highest bit-density figures for early 1α parts (0.315 Gb/mm² on an 8 Gb DDR4 die). SK Hynix’s 24 Gb 1a DDR5 die achieved a significant density jump from 16 Gb 1y-node parts and enabled 48 GB / 96 GB modules. Power reductions were comparable across vendors: SK Hynix quoted 20 percent lower power on LPDDR4 and 25 percent lower system power on 24 Gb DDR5 modules. Speed claims were also similar, with all three companies reaching the top of the then-current LPDDR4 and early DDR5 specifications. Independent analyses showed cell-size and pitch differences of only a few nanometers, confirming that the nodes were closely matched.

Market and Strategic Position

SK Hynix used the 1a node to strengthen its position in two high-volume segments simultaneously: mobile LPDDR (where it already held a strong share) and emerging DDR5 server memory (where it had launched the industry’s first DDR5 products in 2020). The high-yield EUV process helped the company increase output during the 2021 supply shortage and later convert 1a lines to 1b/1c as HBM demand grew. Samsung maintained the largest overall DRAM capacity, while Micron emphasized design-rule leadership and later EUV insertion. By 2024–2025 the competitive focus had shifted to 1c-node and HBM products, but the 1a generation established SK Hynix as a reliable, cost-competitive supplier of both mobile and high-density server DRAM.

In short, SK Hynix did not lead every technical metric on the 1a node, yet its combination of timely EUV deployment, strong yields, and rapid product diversification kept it firmly in the first tier of DRAM manufacturers throughout the fourth-generation 10 nm-class era.

6) Broader Impact and Evolution

SK Hynix’s 1a DRAM node produced effects that extended well beyond a single process generation. It increased industry supply during a tight market, established EUV as a routine DRAM manufacturing tool at the company, and supplied the process platform that later 1b and 1c nodes refined. Those later nodes, in turn, enabled higher-bandwidth products such as HBM3E/HBM4 and LPDDR6 while the company prepared architectural shifts toward 4F² vertical-gate transistors and 3D DRAM.

Immediate Market and Supply Impact

The 25 percent wafer-productivity gain arrived in mid-2021, when DRAM demand from smartphones, PCs, and early data-center DDR5 deployments was still strong. Extra bits per wafer helped SK Hynix raise output without a commensurate increase in capital spending and contributed to easing the supply tightness that had persisted from 2020. The same productivity improvement also lowered manufacturing energy per bit, supporting the company’s ESG reporting. End customers saw the benefits as longer smartphone battery life and higher-capacity, lower-power server DIMMs.

Process Learning That Enabled Later Nodes

1a served as SK Hynix’s first high-volume EUV DRAM platform. The company began with a single EUV layer and then systematically increased the count:

1a: 1 EUV layer
1b: approximately 4 layers
1c: 5 or more layers

Each increment reduced multi-patterning complexity and improved overlay control. Circuit and materials optimizations first qualified on 1a (sense-amplifier design, capacitor dielectric stacks, interconnect resistance) were carried forward and further refined. As a result, the 1c node, introduced in 2024, delivered an additional 11 percent speed increase and more than 9 percent power-efficiency improvement over 1b while remaining on the same 6F² BCAT architecture. SK Hynix applied 1c technology across DDR5, LPDDR, and as the base die for advanced HBM stacks.

Product-Line Expansion

The 1a process quickly moved from mobile LPDDR4 into 24 Gb DDR5, CXL memory modules, and early HBM base dies. Subsequent nodes built on that foundation:

1b enabled higher-density server DIMMs and the first volume HBM3E.
1c supported LPDDR6 development, 192 GB SOCAMM2 modules, and HBM4 preparation.

This continuity allowed SK Hynix to keep existing 1a capacity running as a cost-effective workhorse while converting selected lines to newer nodes as HBM demand accelerated. The approach maximized return on the original EUV investment.

Longer-Term Architectural Transition

By 2025 SK Hynix publicly stated that conventional 6F² planar scaling would become impractical below approximately 10 nm. The company therefore outlined two next steps:

4F² vertical-gate (VG) transistors to shrink cell area by roughly 30 percent while improving performance and power.
True 3D-stacked DRAM for still-higher density once 4F² reaches its limits.

High-NA EUV tools, first installed at the M16 fab in 2025, are intended to support these future nodes. The 1a generation therefore sits at a hinge point: it proved that EUV could be used profitably in DRAM, generated the process knowledge needed for 1b/1c, and bought the industry several more years of 6F² scaling while the more radical 4F² and 3D architectures were developed.

In practical terms, the 1a node did not redefine DRAM architecture, yet it delivered enough incremental density, cost, and efficiency improvement to keep Moore’s-law-style bit-cost reduction alive through the mid-2020s and to position SK Hynix for the next wave of AI-driven memory demand.