SK Hynix’s 1b (1β/1-Beta) DRAM node represents the company’s fifth-generation 10 nm-class process technology, a critical step in DRAM scaling that delivered industry-leading speed, power efficiency, and density when introduced.
DRAM Node Naming and the 10 nm-Class Progression
DRAM manufacturers label successive shrinks within the 10 nm class using alphanumeric or Greek-letter designations rather than a single “nm” figure, because the actual half-pitch (feature size) sits in a range rather than a precise number. SK Hynix’s sequence runs:
- 1x (first-generation ~18 nm)
- 1y (~17 nm)
- 1z (~15–16 nm)
- 1a (fourth-generation, ~13–14 nm)
- 1b / 1β (fifth-generation, ~12–13 nm class)
- 1c (sixth-generation, ~11–12 nm)
The 1b node therefore sits in the mid-12 nm design-rule range. Independent analysis places SK Hynix’s 1b feature size at approximately 12.6 nm.
This generation marked the point at which further scaling required both new materials (High-K Metal Gate, or HKMG) and tighter process control to maintain cell capacitance and sensing margins while shrinking the 6F² cell.
Development Timeline and Official Launch
SK Hynix completed 1b process development in 2023 and publicly announced it on 30 May 2023. The company supplied 16 Gb DDR5 samples to Intel for compatibility validation on Xeon Scalable platforms—the industry’s first 1b-node DDR5 to enter that program. Mass production of 1b DDR5 began in the second half of 2023, giving SK Hynix a first-mover advantage at the time.
The same node was subsequently applied to LPDDR5T mobile DRAM and HBM3E high-bandwidth memory, with HBM3E samples targeted for late 2023 and volume production in 2024. By 2025–2026 the mature 1b process remained the workhorse for HBM3E and early HBM4 core dies, while the company extended the 1b platform to accelerate 1c development.
Core Technical Features and Process Innovations
The 1b node introduced several process and design changes that improved both performance and manufacturability:
- High-K Metal Gate (HKMG): A high-dielectric-constant insulator in the transistor gate stack reduces leakage current and increases capacitance. SK Hynix first commercialized HKMG on mobile DRAM and then brought it to server DDR5 on 1b, cutting power consumption more than 20 % versus the preceding 1a node.
- Cell architecture: 6F² buried-channel-array-transistor (BCAT) cells with refined capacitor structures (quasi-cylindrical or pillar variants) and optimized high-k dielectrics (ZrO/HfAlO stacks). TechInsights measurements show an SK Hynix 1b 16 Gb DDR5 die of 37.98 mm², a cell size of 0.00125 µm², and bit density of 431.40 Mb/mm². Word-line and bit-line pitches measure 33.1 nm and 37.9 nm respectively.
- Lithography: EUV lithography is used on selected critical layers (building on its introduction at 1a), reducing multi-patterning complexity compared with earlier DUV-only flows. Later High-NA EUV tools have been installed for subsequent nodes, but 1b itself relies on a mix of advanced DUV and selective EUV.
These changes delivered a smaller die, higher bit density, and better electrical characteristics without a complete cell-architecture overhaul.
Performance Gains Versus the 1a Node
Compared with SK Hynix’s own 1a-generation DDR5:
- Data-rate increased 14 % (6.4 Gbps versus prior products; 33 % faster than early DDR5 test chips that ran at 4.8 Gbps).
- Power consumption dropped more than 20 % thanks to HKMG.
- The resulting modules offered the industry’s highest DDR5 speed at the time of introduction while improving energy efficiency—an important metric for data-center operators facing rising electricity costs.
Later 1c products built on the 1b platform added another 11 % speed (reaching 8 Gbps) and more than 9 % additional power-efficiency improvement, illustrating the incremental but consistent gains typical of late-10 nm-class scaling.
Products Powered by the 1b Node
The 1b process has been used across multiple product families:
- Server DDR5: 16 Gb (and later higher-density) RDIMMs running at 6.4 Gbps, validated with Intel Xeon platforms. These modules remain widely deployed in 2026 data centers.
- HBM3E and HBM4: SK Hynix’s HBM3E (8 Gbps, 8-Hi and 12-Hi stacks) and first-generation HBM4 core dies use 1b DRAM. The company adopted its proven Advanced MR-MUF stacking process on these products to control warpage and improve thermal performance. HBM4 samples using 1b were delivered in 2025, with volume ramping into 2026.
- Mobile LPDDR5T / LPDDR5X: High-speed, low-power parts for smartphones and edge-AI devices.
The node’s maturity and yield stability made it the preferred choice for high-volume, high-reliability applications such as AI accelerators while 1c ramped.
Competitive Comparison: SK Hynix 1b versus Samsung D1b and Micron 1β
Third-party physical analysis (TechInsights, 2025) provides a side-by-side view of the three vendors’ fifth-generation 10 nm-class cells:
| Parameter | SK Hynix 1b (DDR5 16 Gb) | Samsung D1b (LPDDR5X 16 Gb) | Micron 1β (LPDDR5 16 Gb) |
|---|---|---|---|
| Die size | 37.98 mm² | 36.68 mm² | 36.78 mm² |
| Bit density | 431.40 Mb/mm² | 446.67 Mb/mm² | 435.0 Mb/mm² |
| Cell size | 0.00125 µm² | 0.00123 µm² | 0.00133 µm² |
| Feature size (F) | 12.6 nm | 12.5 nm | 13.1 nm |
| Active / WL / BL pitch | 23.4 / 33.1 / 37.9 nm | 23.5 / 32.6 / 37.6 nm | 24.0 / 34.0 / 39.0 nm |
Samsung achieved a slightly smaller cell and higher density; SK Hynix sits in the middle with a well-balanced design that prioritized yield and HBM stacking compatibility; Micron’s 1β cell is modestly larger. All three vendors use TiN/poly word-line materials and similar high-k capacitor stacks, indicating convergent process choices at this node.
SK Hynix’s strength has been rapid transfer of the 1b platform into high-volume HBM production and early Intel validation, rather than the absolute smallest cell.
Manufacturing Scale and Role in the AI Memory Boom
By 2025–2026 SK Hynix was expanding 1b capacity at existing Icheon fabs (M16) and new Cheongju facilities (M15X pilot line). The node’s maturity allowed the company to prioritize HBM output—where margins are several times higher than commodity DRAM—while still serving server DDR5 demand. Reports in 2025 noted a strategic focus on 1b for HBM3E/HBM4 rather than an immediate full conversion to 1c, reflecting the high utilization and proven reliability of the fifth-generation process.
This positioning helped SK Hynix maintain a leading share of the HBM market (often cited above 50–60 % in 2025–early 2026) even as Samsung and Micron ramped competing offerings.
Transition to 1c and Longer-Term Outlook
SK Hynix deliberately reused the 1b design and process platform to develop 1c, shortening the development cycle by two months and reducing technical risk. The 1c node (low-11 nm class) entered volume production in 2025 and is being applied to later HBM4E, LPDDR6/7, and next-generation DDR5. Beyond 1c the industry faces the physical limits of conventional 6F² planar cells; SK Hynix has publicly discussed a shift toward 4F² vertical-gate and 3D DRAM architectures later in the decade.
High-NA EUV tools installed in 2025 at the M16 fab are intended to support these future shrinks, but 1b itself remains a high-volume, cost-effective workhorse in 2026.
In summary, the 1b node was the generation that first combined HKMG, refined EUV usage, and a well-optimized 12.6 nm-class cell into products that simultaneously delivered higher speed, lower power, and the stacking reliability needed for HBM. It cemented SK Hynix’s position in both conventional server DRAM and the exploding AI-memory market, while serving as the proven foundation for the subsequent 1c generation.
1) DRAM Node Naming and the 10 nm-Class Progression
DRAM node naming follows a generation-based system rather than a single advertised nanometer figure, which often confuses readers accustomed to logic-process names such as “3 nm” or “18A.” The core question is how the industry (SK Hynix, Samsung, and Micron) labels successive shrinks inside the 10 nm class, what those labels actually correspond to in physical dimensions, and why this alphanumeric/Greek-letter convention exists. The system is internally consistent across vendors even though exact feature sizes differ slightly by company and product type.
Why DRAM Uses Generation Names Instead of Exact Nanometers
Logic foundries long ago decoupled marketing node names from any single physical dimension. DRAM manufacturers did something similar but retained a looser link to the half-pitch of the active area (the smallest repeating feature in the memory-cell array).
Once processes entered the 10–20 nm range around 2016–2018, further shrinks became incremental and vendor-specific. Publishing a precise “12.6 nm” number would have been both technically imprecise (different pitches exist for word-line, bit-line, and active area) and commercially awkward. The industry therefore adopted a simple sequential scheme:
- Start with 1x as the first 10 nm-class generation.
- Increment the letter for each subsequent generation.
- When the Latin alphabet ran out after 1z, SK Hynix and Samsung continued with 1a, 1b, 1c… while Micron switched to Greek letters (1α, 1β, 1γ).
The two systems are equivalent: 1a ≈ 1α, 1b ≈ 1β, 1c ≈ 1γ. Each new letter represents a full process generation that typically delivers 15–25 % higher bit density, modestly higher speed, and better power efficiency.
The 10 nm-Class Progression
The table below summarizes the commonly accepted mapping used by industry analysts and the vendors themselves. “Approximate feature size” refers to the design-rule or half-pitch range; actual measured values from teardowns vary by a few tenths of a nanometer between companies.
| Generation | SK Hynix / Samsung | Micron | Approx. Feature Size | Typical Status (2026) | Notes |
|---|---|---|---|---|---|
| 1st | 1x | 1x | ~18 nm | Legacy, largely phased out | First 10 nm-class node |
| 2nd | 1y | 1y | ~16–17 nm | Mature, still in some DDR4 | Pre-EUV for most vendors |
| 3rd | 1z | 1z | ~14–15 nm | Mature volume | Samsung first used EUV here |
| 4th | 1a | 1α | ~13–14 nm | High-volume workhorse | First widespread EUV + HKMG |
| 5th | 1b | 1β | ~12–13 nm | High-volume (HBM3E/HBM4 core) | SK Hynix 1b focus of prior discussion |
| 6th | 1c | 1γ | ~11–12 nm | Leading-edge volume | Current performance leader |
| 7th | 1d | 1δ | ~10–11 nm | Early production / development | Approaching planar-cell limit |
These ranges are consensus figures drawn from vendor statements and third-party analyses; they are not official specifications. Samsung has historically achieved slightly smaller cells at equivalent generations, while Micron’s 1β cell was measured a few tenths of a nanometer larger than SK Hynix’s 1b.
How the Names Map to Real Silicon
Independent physical analysis (primarily TechInsights) provides concrete numbers for recent nodes:
- SK Hynix 1b (16 Gb DDR5): feature size ≈ 12.6 nm, cell size 0.00125 µm².
- Samsung D1b (16 Gb LPDDR5X): feature size ≈ 12.5 nm, cell size 0.00123 µm².
- Micron 1β: feature size ≈ 13.1 nm, cell size 0.00133 µm².
The shrink factor (how much the design rule decreases from one generation to the next) has risen above 0.9 in recent nodes, meaning each step is smaller than the classic 0.7× scaling of earlier decades. This is why the industry talks about “sixth-generation 10 nm-class” rather than claiming a new 11 nm or 10 nm node.
Vendor Differences in Naming and Timing
- SK Hynix and Samsung use the Latin-letter sequence (1a, 1b, 1c) and frequently describe a node as “the fifth-generation of the 10-nanometer process technology.”
- Micron uses Greek letters after 1z and was first to ship 1α (2021) and 1β (2022).
- Timing is not perfectly synchronized. Micron led early 1α/1β volume; SK Hynix led early 1b HBM qualification; Samsung has often shown the smallest cell at a given generation.
All three vendors are now in high-volume 1c/1γ production, with 1d/1δ samples or early wafers appearing in 2026.
Why Scaling Slows After 1c
The 6F² planar cell that has been used for more than a decade is approaching physical limits around 10 nm. Capacitor aspect ratios, contact alignment, and sense-amplifier margins become extremely difficult. Vendors are therefore preparing two architectural shifts:
- 4F² vertical-channel transistor (VCT) cells (Samsung targeting 10a, SK Hynix later).
- True 3D DRAM stacking.
Until those architectures arrive, the 1b–1c–1d sequence remains the practical roadmap for both commodity DRAM and HBM core dies.
In short, the 1x–1y–1z–1a–1b–1c naming system is simply a generation counter inside the 10 nm class. Each letter represents a full process node with measurable improvements in density and efficiency, even if the exact nanometer figure is no longer advertised. The 1b node discussed previously sits squarely in the middle of this mature, high-volume era.
2) Development Timeline and Official Launch
The development and official launch of SK Hynix’s 1b DRAM node followed a compressed, risk-managed path that leveraged the company’s preceding 1a generation. The query focuses on the chronological sequence of internal development, first customer samples, public announcement, validation, and the start of volume production for this fifth-generation 10 nm-class process. While exact internal start dates for process integration remain undisclosed, public milestones from 2023 onward are well documented through company statements and industry reports.
Pre-1b Context: Building on the 1a Foundation
SK Hynix had already established a pattern of being first to Intel validation with its 1a (fourth-generation) DDR5 in January 2023. That success reduced technical risk for the next shrink. The company treated 1b as an evolutionary extension of the 1a platform rather than a complete redesign, which later allowed it to reuse much of the same design and process infrastructure when developing 1c.
Key Milestones in 1b Development and Launch
The following table captures the publicly confirmed dates and events:
| Date | Milestone | Significance |
|---|---|---|
| January 2023 | 1a DDR5 receives first-in-industry Intel Xeon validation | Establishes the validation playbook used for 1b |
| April 2023 | First 1b DDR5 samples delivered to Intel | Earliest known external shipment of 1b silicon |
| May 30, 2023 | Official announcement of 1b development completion + start of Intel validation | Public launch of the fifth-generation 10 nm-class node |
| 2H 2023 | Mass production of 1b DDR5 begins | Industry-first volume production of a 1b-class node |
| 1H 2024 | 1b process applied to LPDDR5T and HBM3E | Broadening beyond server DDR5 |
| 2025 | 1b core dies used in first HBM4 products | Continues as workhorse for high-bandwidth memory |
| 2025–2026 | Capacity expansions at M16 (Icheon) and M15X (Cheongju) | Supports HBM4 volume ramp |
The May 30, 2023 press release remains the definitive public launch date. In it, SK Hynix stated it had “completed the development of the industry’s most advanced 1bnm, the fifth-generation of the 10 nm process technology” and that Intel had begun joint evaluation under the Data Center Certified memory program. The same announcement set the mass-production target for the second half of 2023.
What the Official Launch Communicated
The May 2023 announcement highlighted three immediate claims:
- 6.4 Gbps operating speed — described at the time as the fastest DDR5 in the industry.
- More than 20 % lower power consumption versus 1a DDR5, enabled by the first use of High-K Metal Gate (HKMG) on server DRAM.
- Plans to extend the same process to LPDDR5T and HBM3E in the first half of 2024.
Intel’s public comment at the time confirmed that the 1b samples were the first of their generation targeted at the next Xeon Scalable platform. This early alignment with a major CPU vendor was a deliberate strategy to accelerate qualification and design-win cycles.
Post-Launch Ramp and Product Expansion
Mass production of 1b DDR5 started on schedule in the second half of 2023. By mid-2024 the same process was already feeding HBM3E stacks. In 2025 SK Hynix explicitly cited the mature 1b node as the DRAM core for its first HBM4 products, choosing process stability over an immediate jump to 1c in order to minimize yield and reliability risk on the more complex stacked packages. Capacity conversions at existing Icheon lines and the new M15X fab in Cheongju were executed throughout 2025–2026 specifically to support this HBM demand.
The 1b node therefore moved from first silicon in April 2023 to high-volume, multi-product status within roughly 18 months — a relatively fast cycle by DRAM standards and one that later enabled the accelerated 1c development that reused the same platform.
3) Core Technical Features and Process Innovations
SK Hynix’s 1b DRAM node introduced a set of targeted process and materials innovations that improved power efficiency, cell reliability, and manufacturing yield while continuing 6F² planar cell scaling. The query focuses on the core technical features that defined this fifth-generation 10 nm-class process—particularly High-K Metal Gate adoption, refined cell architecture, capacitor integration, and selective EUV usage. These advances were evolutionary rather than revolutionary, building directly on the 1a platform to deliver measurable gains without a full architectural overhaul.
High-K Metal Gate (HKMG): The Primary Electrical Innovation
The most widely highlighted process change on the 1b node was the extension of High-K Metal Gate technology from mobile DRAM into server-class DDR5.
Traditional SiON gate dielectrics suffered increasing leakage as film thickness shrank. HKMG replaces the insulator with a high-permittivity (High-K) material while switching the gate electrode from polysilicon to metal. The High-K film stores roughly five times more charge than an equivalent-thickness SiON layer, allowing thinner physical films, lower leakage, and higher effective capacitance.
SK Hynix first commercialized HKMG on LPDDR5X in late 2022 and then applied it to 1b DDR5. The result was more than 20 % lower power consumption compared with the preceding 1a DDR5 generation, alongside the ability to reach 6.4 Gbps data rates. This combination of speed and efficiency proved especially valuable for data-center modules and later for HBM core dies.
Cell Architecture and Critical Dimensions
The 1b node retained the industry-standard 6F² buried-channel-array-transistor (BCAT) layout. Independent physical analysis of a 16 Gb DDR5 die yields the following measured values:
| Parameter | SK Hynix 1b Value |
|---|---|
| Feature size (F / design rule) | ≈ 12.6 nm |
| Cell size | 0.00125 µm² |
| Bit density | 431.40 Mb/mm² |
| Die size (16 Gb) | 37.98 mm² |
| Active island length | 84 nm |
| Active / Word-line / Bit-line pitch | 23.4 / 33.1 / 37.9 nm |
| Word-line (cell gate) materials | TiN / Poly |
| Smallest periphery gate pitch | 130 nm |
These dimensions place the node firmly in the mid-12 nm class. The modest shrink relative to 1a still produced a meaningful density increase while preserving enough process margin for high-volume manufacturing and subsequent stacking into HBM packages.
Capacitor Structure and Dielectric Stack
Maintaining adequate cell capacitance (typically targeted above 6–7 fF) becomes progressively harder as lateral dimensions shrink. On 1b, SK Hynix continued the transition toward quasi-cylindrical or optimized storage-node structures that had begun in earlier generations.
Key observed features include:
- Circular storage-node landing pad (SNLP) shape.
- Self-aligned contact (SAC) etch for the storage-node contact.
- Multi-layer high-k dielectric stack detected as ZrO / HfAlO / ZrAlO / HfAlO / ZrAlO.
- Top-plate materials of W / SiGe (approximately 54 nm / 95 nm) on TiN.
These material and structural refinements helped preserve sensing margin and reliability despite the smaller cell footprint. The same capacitor platform later served as a stable foundation when the company extended the 1b process flow into 1c development.
Lithography Strategy: Selective EUV Plus Advanced DUV
SK Hynix first introduced EUV lithography on the 1a node in 2021. On 1b the company employed a hybrid approach—selective EUV on the most critical layers combined with high-precision DUV multipatterning on others.
This hybrid strategy reduced the total number of masking steps relative to a pure multi-patterning DUV flow, improved pattern fidelity, and supported higher wafer-level yields. Full High-NA EUV systems arrived later (installed for mass production at M16 in 2025) and were aimed primarily at subsequent nodes; 1b itself relied on the mature Low-NA EUV tools already in the fleet.
Metallization and Peripheral Design
The 1b die typically uses a five-layer metal stack (one tungsten, three copper, one aluminum) plus a redistribution layer. Bit-line interconnection is handled at the M1 level. Peripheral circuitry shows a smallest gate pitch of approximately 130 nm—somewhat more conservative than the densest competitors at the same generation—reflecting a design emphasis on yield and reliability for high-volume server and HBM applications.
Performance and Manufacturability Impact
Taken together, the innovations delivered:
- 20 % power reduction versus 1a DDR5.
- Industry-leading 6.4 Gbps DDR5 speeds at the time of launch.
- Sufficient process maturity to serve as the core die for both HBM3E and first-generation HBM4 products.
- A reusable platform that shortened 1c development by roughly two months.
In short, the 1b node’s technical contribution was not a single breakthrough but a carefully balanced set of materials, structural, and lithography refinements that kept planar 6F² DRAM competitive while preparing the manufacturing base for the more aggressive shrinks that followed.
4) Performance Gains Versus the 1a Node
SK Hynix’s 1b node delivered clear, measurable gains over the preceding 1a generation in both speed and power efficiency, which were the two metrics the company emphasized at launch. The comparison focuses on 16 Gb-class DDR5 products, the first volume application of each node, because that is where official figures were published. Gains in other product families (LPDDR and HBM) followed the same process improvements but were not always quantified in the same press materials.
Official Performance Claims at Launch
In its May 2023 announcement, SK Hynix stated that 1b DDR5 products supplied to Intel ran at 6.4 Gbps. That figure represented:
- A 33 % increase versus early DDR5 test chips that operated at 4.8 Gbps.
- A 14 % increase versus the company’s own prior-generation 1a DDR5 parts.
- More than 20 % lower power consumption than 1a DDR5, attributed primarily to the first use of High-K Metal Gate (HKMG) on server DRAM.
These numbers were presented as industry-leading at the time of introduction.
Side-by-Side Comparison
The table below summarizes the publicly disclosed differences between the two consecutive SK Hynix nodes for DDR5:
| Metric | 1a Node (4th-gen 10 nm-class) | 1b Node (5th-gen 10 nm-class) | Improvement |
|---|---|---|---|
| Typical DDR5 data rate | ~5.6–6.0 Gbps range | 6.4 Gbps | +14 % |
| Power consumption (vs prior) | Baseline | >20 % reduction | >20 % lower |
| Feature size (approx.) | ~13–14 nm | ~12.6 nm | Modest shrink |
| Key enabling process | EUV on selected layers | EUV + first server HKMG | Materials + design |
The speed gain came from a combination of the smaller cell, improved sensing margins, and circuit-density optimizations. The larger power saving was driven by the HKMG transistor stack, which reduced leakage while maintaining or increasing capacitance.
How the Gains Were Achieved
- HKMG transistor: Replacing the conventional SiON insulator with a high-k dielectric plus a metal gate cut leakage current and allowed a thinner effective oxide. This directly translated into the >20 % power reduction while still supporting the higher operating frequency.
- Cell shrink and design tweaks: The move from ~13–14 nm to ~12.6 nm feature size, together with higher circuit density and enhanced sense-amplifier performance, raised data-processing speed without a proportional increase in voltage or current.
- Process maturity carry-over: Because 1b reused much of the 1a platform, SK Hynix could focus engineering effort on electrical optimization rather than solving an entirely new set of integration problems.
Later internal comparisons (when 1c was announced) showed that 1b itself still had headroom: the subsequent node added another 11 % in speed and more than 9 % in power efficiency on top of the 1b baseline. That incremental improvement underscores that 1b was a solid but not final step in the late-10 nm-class era.
Practical Impact
For data-center operators the combination of higher bandwidth and lower energy per bit reduced both performance bottlenecks and electricity costs. The same process advantages later allowed 1b dies to serve as reliable core chips for HBM3E and first-generation HBM4 stacks, where thermal and power budgets are even tighter than in conventional DIMMs.
In short, the 1b node’s performance story versus 1a is straightforward: modestly higher speed plus a substantial drop in power, enabled mainly by HKMG and a well-controlled shrink of an already mature platform.
5) Products Powered by the 1b Node
The 1b node powered a broad portfolio of SK Hynix products spanning server DDR5, high-bandwidth memory for AI accelerators, and mobile DRAM. Because the process combined solid electrical performance with high manufacturing maturity, the company used it as a workhorse node for several years rather than treating it as a short-lived shrink. The same silicon appeared in both conventional DIMMs and stacked HBM packages.
Server DDR5 Modules
The first volume products were 16 Gb DDR5 chips running at 6.4 Gbps. These were assembled into RDIMMs and later into higher-capacity modules.
By late 2025 SK Hynix had moved to 32 Gb 1b dies that enabled 256 GB DDR5 RDIMMs. That module became the first 32 Gb-die 256 GB part to complete Intel Data Center Certification for the Xeon 6 platform. Compared with earlier 16 Gb 1a-based 256 GB modules, the new design delivered roughly 16 % higher inference performance and about 18 % lower power. The same 1b dies also appeared in MRDIMM and 3DS (TSV-stacked) configurations aimed at high-density AI servers.
High-Bandwidth Memory (HBM3E and HBM4)
HBM became the highest-volume and highest-margin application of the 1b process.
- HBM3E: SK Hynix used 1b DRAM for both 8-Hi (24 GB) and 12-Hi (36 GB) stacks. Mass production of the 12-layer version began in 2024. These stacks powered NVIDIA H200, B100/B200, and GB200 systems and remained in high-volume shipment through 2025–2026.
- HBM4: The first-generation HBM4 products also used 1b core dies (the logic base die was typically manufactured by TSMC). SK Hynix chose the mature 1b process for HBM4 to minimize yield and reliability risk on the more complex 12-layer (and later 16-layer) packages. 12-layer HBM4 samples shipped in 2025, with volume production ramping in the second half of that year and into 2026. The company reserved the newer 1c node for subsequent HBM4E products.
This dual use of 1b for both HBM3E and early HBM4 allowed SK Hynix to scale output quickly while competitors were still qualifying later nodes.
Mobile and Low-Power DRAM
The same process was applied to LPDDR5T and LPDDR5X parts beginning in the first half of 2024. These chips leveraged the HKMG transistor stack already proven on 1b server DRAM to deliver high speed and low power for smartphones and emerging on-device AI applications.
Product Summary
| Product Family | Key Configurations | Role of 1b Node | Timeframe |
|---|---|---|---|
| DDR5 Server | 16 Gb → 32 Gb dies, RDIMM/MRDIMM/3DS | Primary process for high-capacity modules | 2023–2026 |
| HBM3E | 8-Hi 24 GB, 12-Hi 36 GB | Core DRAM die | 2024–2026 volume |
| HBM4 (first gen) | 12-Hi (later 16-Hi) | Core DRAM die (logic base die separate) | Samples 2025, MP 2025–26 |
| LPDDR5T / LPDDR5X | High-speed mobile | Low-power, high-speed variants | From 1H 2024 |
The 1b node therefore served as the common manufacturing foundation for SK Hynix’s most important product lines during the mid-2020s AI memory expansion. Its combination of proven yield, adequate density, and strong power efficiency made it the practical choice for both high-volume commodity DRAM and the more demanding stacked-memory applications.
6) Manufacturing Scale and Role in the AI Memory Boom
The 1b node became SK Hynix’s primary high-volume manufacturing platform during the mid-2020s AI memory surge, supplying the core dies for both HBM3E and first-generation HBM4 while conventional DDR5 demand also remained strong. Its process maturity allowed the company to convert and expand capacity quickly without the yield risks associated with jumping immediately to the next shrink.
Capacity Strategy and Fab Utilization
SK Hynix treated 1b as a stable, high-yield workhorse rather than a transitional node. Existing Icheon facilities (particularly M16, already equipped for EUV) were upgraded or converted to increase 1b output. The new M15X extension in Cheongju was designed from the outset for next-generation DRAM and HBM, with wafer input beginning in the first quarter of 2026. Initial capacity targets started in the low tens of thousands of wafers per month and were planned to ramp toward 55,000–80,000 wafers per month as additional cleanrooms came online.
A significant share of total DRAM wafer starts—estimated around 30 % and rising—was allocated to HBM production. Because HBM stacking and TSV processing use dedicated backend lines, this allocation was not easily interchangeable with commodity DDR5 output. The 1b process’s proven reliability made it the preferred choice for these high-value stacked products.
Role in the HBM Boom
HBM3E (8-Hi and 12-Hi) and the first HBM4 stacks both used 1b core dies. This decision let SK Hynix scale output rapidly after NVIDIA and other accelerator vendors qualified the parts. The company maintained a leading HBM market share, frequently reported in the mid-to-high 50 % range through 2025 and early 2026, even as overall DRAM revenue share fluctuated with commodity pricing cycles.
The economic impact was substantial. HBM commanded several times the margin of standard DRAM. Combined with tight supply, this mix helped SK Hynix post record operating margins (reported above 70 % in some 2026 quarters). The 1b node therefore functioned as both a technical and financial foundation for the company’s AI-memory leadership.
Broader Context in the AI Cycle
Explosive demand from hyperscalers and GPU vendors outstripped available supply throughout 2024–2026. SK Hynix responded by prioritizing 1b conversions and the M15X ramp rather than accelerating 1c investment as aggressively as some competitors. The newer 1c node was reserved for later products such as HBM4E, while 1b continued to feed the bulk of near-term HBM volume. Larger greenfield projects (Yongin cluster phases and additional Cheongju capacity) were approved in 2026 but would not add meaningful output until 2027–2029.
In short, the 1b process allowed SK Hynix to convert existing and newly completed cleanrooms into reliable, high-margin HBM capacity at the exact moment AI accelerator demand peaked. Its combination of adequate density, strong power efficiency, and manufacturing predictability made it the practical engine of the company’s mid-decade AI memory expansion.
7) Transition to 1c and Longer-Term Outlook
SK Hynix treated the 1b node as a proven platform rather than an endpoint, using it to accelerate development of the following 1c generation and to buy time for more fundamental architectural changes later in the decade. The transition illustrates both the diminishing returns of late-10 nm-class planar scaling and the company’s strategy of minimizing risk while still advancing performance.
How 1c Built Directly on 1b
When SK Hynix developed 1c (sixth-generation 10 nm-class, roughly 11–12 nm), it explicitly reused the 1b design and process platform. Engineers described this as a way to reduce technical risk and cut development time by about two months compared with a full redesign. Complex modules such as the capacitor were integrated earlier into the mass-production flow rather than being treated as separate development stages.
The resulting 16 Gb 1c DDR5, announced in August 2024, delivered:
- An 11 % increase in operating speed (reaching 8 Gbps versus the 1b baseline).
- More than 9 % improvement in power efficiency.
- A claimed 30 %+ gain in manufacturing productivity through design optimizations that increased net die count.
Mass-production readiness for 1c DDR5 was targeted for late 2024, with volume shipments beginning in 2025. The same node was planned for later HBM4E core dies, LPDDR6/7, and other high-end products, while first-generation HBM4 continued to use the more mature 1b process.
Limits of Further Planar Scaling
Industry analyses indicate that conventional 6F² cells are approaching physical limits around the 10 nm threshold. Capacitor aspect ratios, contact alignment, and sensing margins become extremely difficult to maintain. Shrink factors have already risen above 0.9 in recent generations, meaning each new letter (1c, 1d) delivers smaller relative gains than earlier nodes.
SK Hynix and others have therefore begun discussing two architectural shifts:
- 4F² vertical-channel transistor (VCT) cells, which rearrange the transistor and capacitor to occupy less area.
- True 3D DRAM stacking, moving beyond planar shrinks altogether.
These changes are expected in the late 2020s and early 2030s rather than immediately after 1c.
Lithography and Tooling Outlook
SK Hynix installed the industry’s first commercial High-NA EUV system (ASML EXE:5200B) at its M16 fab in 2025. The tool offers higher resolution (NA 0.55 versus 0.33) and is intended to support the finer features required for 1d and subsequent nodes, as well as to reduce multi-patterning complexity. Full High-NA adoption for volume DRAM production is still several years away; 1c itself continues to rely primarily on existing Low-NA EUV plus advanced DUV.
Longer-Term Product and Capacity Roadmap
Public statements and analyst reports outline the following sequence:
- 2025–2027: 1c ramps in DDR5, LPDDR, and HBM4E; 1b remains the high-volume HBM3E/HBM4 workhorse.
- Late 2020s: 1d (seventh-generation 10 nm-class) and early 4F² or 3D DRAM experiments.
- 2029–2031: Next-generation HBM5, GDDR successors, and more widespread 3D DRAM.
- Capacity: Existing M15X and Icheon lines plus the first Yongin cluster phases (cleanrooms opening 2027 onward) will support both 1c and later nodes. Larger greenfield investments approved in 2026 are not expected to add output until 2028–2029.
In summary, the 1b node served as both a high-volume production workhorse and a stable foundation that allowed SK Hynix to bring 1c to market faster and with lower risk. Beyond 1c the industry faces the end of conventional planar 6F² scaling; the next decade will be defined by new cell architectures and 3D integration rather than simple letter-by-letter shrinks. The 1b generation therefore marks the mature middle of the 10 nm-class era rather than its conclusion.