SK Hynix’s 1z DRAM node represents the company’s third-generation 10 nm-class process technology, announced in 2019 as a high-density, cost-efficient shrink that delivered industry-leading bit density at the time without relying on expensive extreme ultraviolet (EUV) lithography. The query focuses on this specific node’s technical details, advantages, applications, and place in SK Hynix’s DRAM roadmap, which has since progressed through 1a, 1b, and 1c generations. Ambiguities in the original phrasing (a title-like statement) are resolved by treating it as a request for an in-depth technical overview suitable for publication, covering development, specs, comparisons, and evolution rather than a single narrow spec sheet.

This node marked a key milestone in planar 6F² DRAM cell scaling before the industry’s heavier shift to EUV and more complex multi-patterning at later nodes.

Historical Context and Development Timeline

SK Hynix entered the 10 nm-class DRAM era with 1x (first generation) around 2018, followed by 1y (second generation). The 1z node, internally code-named “Riesel” in some references, arrived as the third generation. Development of the flagship 16 Gb DDR4 product completed in October 2019, just 11 months after the 1y generation. Mass production preparations finished by late 2019, with shipments ramping in 2020.

This timing aligned with industry peers: Samsung and Micron also introduced 1z-class products around the same period. SK Hynix emphasized avoiding EUV to maintain cost competitiveness while achieving a 27% productivity gain over 1y through smaller cells and higher wafer output. The node later extended to mobile LPDDR5 and early high-bandwidth memory (HBM3) products. By the mid-2020s, SK Hynix had converted key fabs (such as Wuxi) from 1z to 1a, reflecting the natural node transition as demand shifted toward higher-performance, EUV-enabled generations.

The 10 nm-class designation is marketing terminology common in DRAM. It refers to successive shrinks of the active-area half-pitch and cell dimensions rather than a literal 10 nm transistor feature. Actual measured pitches at 1z were in the mid-40 nm range for word lines and bit lines.

Key Technical Features and Process Innovations

The 1z process used a buried word-line (BWL) architecture with a buried cell array transistor (BCAT). This places the access transistor below the silicon surface to reduce interference and enable tighter pitches compared with earlier saddle-fin or recessed-channel approaches.

TechInsights analyses of production dies provide concrete measurements:

• In a 16 Gb LPDDR5 die (extracted from an iPhone 15 Pro), bit-line pitch measured 47.4 nm and word-line pitch 42.0 nm.
• Cell size reached approximately 0.0020 µm², a roughly 10% reduction versus SK Hynix’s own 1y generation and about 20% versus 1x.
• Bit density on the 16 Gb DDR4 die hit 0.296 Gb/mm²—the highest reported for a 16 Gb DDR4 chip at the time of analysis—with a compact die size around 54 mm².

Backend-of-line (BEOL) used five metal layers (one aluminum, three copper, one tungsten) plus an aluminum redistribution layer. Capacitors employed a quasi-cylindrical structure with high-k dielectrics. SK Hynix introduced a new material not used in the prior generation specifically to maximize cell capacitance, a critical parameter for reliable charge storage and sensing margin as cells shrink. A new circuit design technique improved operational stability.

Importantly, 1z relied on argon-fluoride (ArF) immersion lithography with multi-patterning (self-aligned double patterning and related techniques) rather than EUV. This avoided the high capital cost of EUV scanners while still delivering the shrink. Later nodes (1a onward) adopted EUV for critical layers to manage increasing process complexity.

Performance Metrics and Advantages

The 16 Gb DDR4 1z product supported up to 3,200 Mbps, the maximum specified speed for the DDR4 interface. Power consumption dropped approximately 40% versus equivalent-density modules built from 1y-generation 8 Gb chips. Productivity (chips per wafer) rose 27% thanks to the smaller cell and optimized layout.

These gains stemmed from three main levers:

• Higher bit density per die and per wafer.
• Improved capacitance and sensing from new materials and design.
• Lower operating current from refined transistors and interconnects.

The node’s non-EUV nature provided a cost edge during a period when EUV tools were still ramping and expensive. SK Hynix positioned 1z as the highest-density, highest-speed, and most power-efficient DDR4 offering available at launch.

Product Implementations and Applications

SK Hynix applied 1z across multiple product families:

• DDR4: 16 Gb chips used in server RDIMM/LRDIMM and client modules. These enabled high-capacity modules while keeping power budgets competitive.
• LPDDR5: 16 Gb and 12 Gb dies appeared in smartphones (e.g., Apple iPhone 15 Pro and Huawei devices). The process supported 4,266 Mbps-class speeds with significant power savings versus LPDDR4.
• HBM3: Early 16 Gb HBM3 stacks for NVIDIA Hopper GPUs (Grace Hopper Superchip) used 1z DRAM dies. This was SK Hynix’s first HBM3 offering and delivered over 3 TB/s aggregate bandwidth in multi-stack configurations.

The company stated plans to extend the process to additional LPDDR5 and HBM variants. In practice, 1z served as a bridge node: it supplied volume products while SK Hynix ramped EUV-capable 1a production.

Comparison with Adjacent Nodes and Competitors

The following table summarizes SK Hynix’s 10 nm-class progression (approximate values drawn from public analyses and company statements; exact pitches vary by product):

Generation	Approx. Period	Lithography	Notable Cell Size / Density	Key Change vs. Prior	Typical Products
1x	~2018	DUV multi-patterning	Larger cells	First 10 nm-class entry	Early DDR4/LPDDR4
1y	2018–2019	DUV	~10% larger than 1z	Incremental shrink	DDR4, early LPDDR5
1z	2019–2021+	DUV (no EUV)	~0.0020 µm²; 0.296 Gb/mm² (16 Gb DDR4)	+27% productivity, new capacitor material	16 Gb DDR4, LPDDR5, early HBM3
1a	2021+	Partial EUV	Further shrink, +25% chips/wafer vs 1z	First SK Hynix EUV DRAM	LPDDR4X, later DDR5
1b / 1c	2023–2025+	Broader EUV	~0.00125 µm² range at 1b	Higher speed/efficiency; High-NA EUV evaluation	DDR5, LPDDR5X, HBM3E/HBM4

Versus competitors at the 1z generation, SK Hynix achieved among the highest bit densities on 16 Gb DDR4. Samsung and Micron 1z products showed similar cell-size convergence (around 0.0020–0.0023 µm² range), but SK Hynix’s non-EUV approach differentiated it on cost. Later analyses showed shrink factors becoming harder (above 0.92× at 1z), signaling the approaching limits of 6F² planar cells.

Challenges, Industry Context, and Legacy

DRAM scaling at 1z already faced rising difficulties: smaller capacitors required new high-k materials and process tweaks to maintain sufficient capacitance (typically targeted above 6–7 fF/cell). Row-hammer mitigation, sensing margin, and interconnect resistance also grew more demanding. SK Hynix addressed these with material innovation and design changes rather than immediately adopting EUV.

By 2026 the 1z node is a mature, legacy process. Production has largely migrated to 1a/1b/1c for leading-edge DDR5, LPDDR5X, and HBM products. Remaining 1z capacity supports cost-sensitive or long-lifecycle applications. The node demonstrated that meaningful density and efficiency gains remained possible with DUV multi-patterning, buying time before the industry’s full EUV transition and eventual exploration of 3D DRAM or new cell architectures.

SK Hynix’s 1z work contributed to its later leadership in HBM for AI accelerators and world-first 1c DDR5 development. It illustrated a pragmatic balance of performance, cost, and manufacturability during a period of intensifying competition among the three major DRAM suppliers.

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1) Historical Context and Development Timeline

The historical context and development timeline of SK Hynix’s 1z DRAM node centers on its role as the third-generation 10 nm-class process, announced in late 2019 after a rapid follow-on to the 1y generation. This node arrived during a period when DRAM scaling was already slowing, productivity and cost efficiency were critical amid market cycles, and the industry was approaching the practical limits of DUV multi-patterning before widespread EUV adoption. The query isolates this timeline aspect of the original 1z topic, so the response focuses on preceding nodes, exact announcement and production dates, industry backdrop, and how 1z fit into SK Hynix’s longer miniaturization path.

Broader Miniaturization Path Leading to 10 nm-Class DRAM

SK Hynix’s DRAM scaling followed a consistent pattern of successive shrinks, often with internal code names drawn from stars or constellations. Key earlier milestones included:

• 2006: 60 nm-class.
• 2009: 40 nm-class and world’s first 44 nm DDR3.
• 2010–2011: 30 nm-class, including 2 Gb DDR4.
• 2012–2013: 20 nm-class, including industry-first 20 nm LPDDR4.
• 2018: Entry into 10 nm-class with the 1x generation (code-named Alius).

The company reached the 10 nm class in 2018, later than Samsung (which began 1x mass production of 8 Gb DDR4 in early 2016 using ArF immersion and multi-patterning without EUV). By then, the three major DRAM makers (Samsung, SK Hynix, Micron) had consolidated the market after earlier industry shakeouts. Scaling gains were becoming harder, with shrink factors rising and cell capacitance maintenance growing more challenging. Productivity per wafer and power efficiency became as important as raw density.

1x and 1y Generations: Immediate Precursors

The 1x node marked SK Hynix’s first 10 nm-class DRAM. Details on exact 1x announcement dates are less prominently documented than later nodes, but it preceded the well-publicized 1y work.

The 1y generation (code-named Da Vinci) was formally announced on November 12, 2018, with an 8 Gb DDR4 product. Compared with 1x, it delivered:

• Approximately 20% higher productivity.
• More than 15% lower power consumption.
• Support for 3,200 Mbps (DDR4 maximum).

SK Hynix also developed a 16 Gb DDR5 on 1y in the same November 2018 timeframe. Shipments of 1y DDR4 began in the first quarter of 2019. This generation used refined DUV multi-patterning, 4-phase clocking, and improved sense-amplifier control. It served as the direct baseline for 1z.

Samsung had already moved into 1y mass production earlier (late 2017 for some products), illustrating the typical staggered cadence among the big three.

1z Announcement and Ramp (2019–2020)

SK Hynix announced completion of 1z development on October 21, 2019—only about 11 months after the 1y announcement. The flagship product was a 16 Gb DDR4, described as the industry’s highest-density single-chip DRAM at the time. Key claims included:

• 27% productivity improvement versus 1y.
• No requirement for expensive EUV lithography.
• Up to 3,200 Mbps.
• Roughly 40% lower power versus equivalent-density 1y-based modules.
• New capacitor material and design changes for stability.

Mass-production preparations were targeted for the end of 2019, with full-scale shipments starting in 2020. The node was internally associated with the code name Riesel in some references. SK Hynix immediately signaled plans to apply 1z to LPDDR5 and HBM3, which later materialized.

This rapid 1y-to-1z cycle reflected competitive pressure and the need to extract more bits per wafer during a period of DRAM market volatility. Contemporaneous analyses noted that 1z-era shrink factors were already exceeding 0.92× for the major players, indicating diminishing returns from traditional 6F² cell scaling.

Industry Context Around 2019

The late 2010s saw DRAM makers balancing cyclical oversupply risks with the need to fund next-node R&D. Samsung and Micron also introduced 1z-class products around 2019. All three relied primarily on DUV ArF immersion plus multi-patterning at this stage; EUV was still being qualified or used only selectively. Cost control without EUV scanners was a selling point for SK Hynix’s 1z approach.

The node arrived just as demand for higher-density server and mobile memory was rising, and before the later AI-driven HBM surge that would reshape capacity allocation.

Subsequent Evolution and 1z’s Place in the Roadmap

After 1z, SK Hynix introduced 1a (fourth-generation 10 nm-class, code-named Canopus) with first EUV use in mass production starting July 2021 for LPDDR4 products. This delivered an additional ~25% chips-per-wafer gain versus 1z. Later nodes (1b, 1c) expanded EUV layers and further improved speed and efficiency, culminating in the 2024 world-first 1c 16 Gb DDR5.

By 2026, 1z had become a mature/legacy node. Key fabs such as Wuxi completed conversion from 1z to 1a. Remaining 1z capacity supported cost-sensitive or long-lifecycle products while leading-edge output shifted to 1b/1c and HBM variants.

The 1z timeline illustrates SK Hynix’s pattern of relatively tight generational cadence in the 10 nm-class era (roughly 11–18 months between major announcements) before process complexity and EUV integration lengthened later cycles. It also highlights how the company used material and design innovation to delay full EUV dependency while still delivering measurable density and efficiency gains.

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2) Key Technical Features and Process Innovations

The key technical features and process innovations of SK Hynix’s 1z DRAM node centered on refinements to the established 6F² buried-word-line cell architecture, targeted material changes for capacitance, and continued use of DUV multi-patterning rather than EUV. These choices enabled a meaningful cell-size reduction and productivity gain while controlling cost. The original query’s request for this section of the 1z overview is addressed here with measured data from production dies, process-flow details, and comparison to adjacent generations.

Cell Architecture: Buried Word Line and BCAT

SK Hynix used a buried word-line (BWL) structure in which the word line sits below the silicon surface and forms the gate of a buried cell array transistor (BCAT). This approach, already adopted in earlier 10 nm-class nodes, reduces bit-line-to-word-line capacitive coupling, improves read margin, and allows tighter pitches compared with older saddle-fin or recessed-channel-array-transistor (RCAT) layouts.

Production analyses of a 16 Gb LPDDR5 1z die (from an iPhone 15 Pro) measured:

• Word-line pitch: 42.0 nm
• Bit-line pitch: 47.4 nm

These pitches produced a cell size of approximately 0.0020 µm²—about 10% smaller than SK Hynix’s own 1y generation and roughly 20% smaller than 1x. The resulting bit density on the 16 Gb DDR4 die reached 0.296 Gb/mm², among the highest reported for that density at the time. Active-area islands were formed with shallow-trench isolation, and the overall layout remained 6F².

Bit lines ran under the capacitors (a capacitor-over-bit-line, or COB, arrangement in some descriptions). Storage-node landing pads and plugs connected the capacitors to the cell transistors.

Capacitor Structure and Material Innovation

As cells shrank, maintaining adequate capacitance (typically targeted above 6–7 fF per cell) became the dominant challenge. SK Hynix transitioned from conventional cylindrical capacitors toward a quasi-cylindrical structure, consistent with the company’s 1y-to-1z evolution and similar moves by Samsung at 1z.

High-k dielectric stacks (commonly ZrO₂/AlOₓ or related multi-layer combinations) were used, with dielectric thickness reduced to improve capacitance. The company specifically introduced a new substance not employed in the prior generation “to maximize the capacitance.” This material change, combined with process-integration tweaks, supported reliable charge storage and sensing despite the smaller physical volume. A new circuit-design technique was also applied to improve operational stability and reduce errors.

Sense-amplifier transistors received related updates, including recessed-channel structures in some descriptions, to enhance reliability at the tighter design rules.

Backend-of-Line (BEOL) and Interconnect

The 1z process used five BEOL metal layers:

• One aluminum
• Three copper
• One tungsten

Vias were filled accordingly (tungsten for via 1 and via 4, copper for via 2 and via 3). An aluminum redistribution layer (RDL) completed the stack. This combination provided the necessary current-carrying capability and routing density for both the array and peripheral circuitry while remaining compatible with the DUV-based front-end.

Lithography and Patterning Strategy

A defining feature of 1z was the absence of extreme-ultraviolet (EUV) lithography. The node relied on argon-fluoride (ArF) immersion DUV tools plus multi-patterning techniques such as self-aligned double patterning (SADP). This approach avoided the high capital cost of EUV scanners while still achieving the required pitches.

The decision kept 1z cost-competitive versus contemporaneous 1z products from competitors that were beginning to insert EUV on selected layers. Subsequent SK Hynix nodes (1a onward) adopted EUV for critical layers as shrink factors tightened further and overlay/process-window demands increased.

Supporting Process Elements

Additional features observed or inferred from analyses include:

• Air-gap spacers in some interconnect or isolation regions to reduce parasitic capacitance.
• Optimized storage-node contact and landing-pad processes.
• Continued use of high-k metal-gate or related transistor engineering in peripherals, though the array itself used the buried-gate BCAT.

These elements collectively delivered the 27% productivity increase and 40% power reduction versus equivalent-density 1y modules that SK Hynix highlighted at announcement.

The 1z process therefore represented a mature, well-optimized 6F² planar DRAM flow that extracted additional scaling from existing DUV infrastructure and targeted material/design changes rather than a wholesale architectural shift. It served as a practical bridge before the industry’s broader move to more EUV layers and, eventually, exploration of 4F² or 3D cell concepts at later nodes.

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3) Performance Metrics and Advantages

The performance metrics and advantages of SK Hynix’s 1z DRAM node delivered measurable gains in density, productivity, speed, and power efficiency over the preceding 1y generation while remaining cost-competitive through the absence of EUV lithography. These results were achieved on the 16 Gb DDR4 flagship product and subsequently applied to LPDDR5 and early HBM3. The request for this section of the 1z overview is answered with official claims, third-party die analyses, and contextual comparisons.

Official Performance Claims (16 Gb DDR4 1z)

SK Hynix’s October 2019 announcement highlighted three primary metrics versus the 1y generation:

• Productivity: Approximately 27% more chips per wafer, driven by the smaller cell size and optimized layout.
• Power consumption: About 40% lower than modules of equivalent density built from 1y-generation 8 Gb chips.
• Speed: Up to 3,200 Mbps, matching the maximum specified rate for the DDR4 interface.

The 16 Gb density itself was described as the industry’s highest for a single DRAM chip at the time, which also maximized total bits per wafer. A new capacitor material and design technique supported these gains by improving capacitance and operational stability.

Die-Level Metrics from Independent Analyses

TechInsights examination of production 16 Gb DDR4 1z dies (H5ANAG8NCJR-XNC and related parts) confirmed:

• Bit density of 0.296 Gb/mm² — the highest reported for a 16 Gb DDR4 device at the time of analysis.
• Smallest die size among contemporaneous 16 Gb DDR4 products.

A 16 Gb LPDDR5 1z die used in the iPhone 15 Pro showed word-line and bit-line pitches of 42.0 nm and 47.4 nm, respectively, consistent with the cell-size reduction that enabled the density improvement. A 12 Gb LPDDR4X 1z example demonstrated 4,266 Mbps operation and substantial power savings relative to prior LPDDR4 interfaces (approximately 45% lower energy for I/O operations in one comparison).

These figures translated into practical system-level benefits: higher-capacity modules at given power envelopes for servers and longer battery life or thermal headroom in mobile devices.

Comparison Table: 1y versus 1z (SK Hynix)

Metric	1y Generation	1z Generation	Improvement
Flagship density	8 Gb / 16 Gb DDR4	16 Gb DDR4 (highest single-chip)	Higher capacity
Productivity (chips/wafer)	Baseline	+27%	Significant
Power (equiv. density modules)	Baseline	~40% lower	Major efficiency
DDR4 speed	Up to 3,200 Mbps	Up to 3,200 Mbps	Matched max spec
Bit density (16 Gb DDR4)	Lower	0.296 Gb/mm²	Highest at launch
Lithography	DUV multi-patterning	DUV multi-patterning (no EUV)	Cost advantage

Later nodes continued the trend: 1a added roughly 25% more chips per wafer versus 1z, while 1c delivered an 11% speed increase and 9% power-efficiency gain versus 1b. The 1z results therefore represented a solid incremental step rather than a revolutionary leap.

Strategic and Cost Advantages

The decision to forgo EUV kept capital and process-complexity costs lower than competitors that were inserting EUV on selected layers at 1z. Combined with the 27% productivity lift, this improved SK Hynix’s cost position during a cyclical DRAM market. The power reduction was especially valuable for high-density server RDIMM/LRDIMM modules and mobile LPDDR products, where energy and thermal constraints are tight.

In HBM3 implementations, the 1z dies enabled SK Hynix’s first HBM3 stacks, supporting over 3 TB/s aggregate bandwidth in multi-stack GPU packages such as NVIDIA’s Hopper platform.

Overall, 1z provided a balanced combination of higher bit output, lower power, and contained manufacturing cost that helped SK Hynix compete effectively until EUV-enabled 1a and later nodes became the volume mainstream.

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4) Product Implementations and Applications

SK Hynix applied the 1z DRAM node across DDR4, LPDDR5/LPDDR4X, and early HBM3 products, enabling higher-density server modules, power-efficient smartphone memory, and the company’s first high-bandwidth memory stacks for AI accelerators. The request for this section of the 1z overview covers specific implementations, device examples confirmed by teardown analyses, and the end markets they served.

DDR4 Implementations

The flagship 16 Gb DDR4 1z chip (examples include H5ANAG8NCJR-XNC and related markings) was used in both server and client modules. It supported the maximum 3,200 Mbps DDR4 data rate and allowed higher-capacity RDIMM and LRDIMM configurations while keeping power budgets competitive. SK Hynix had previously offered 128 GB and 256 GB high-density modules on 1y; the 1z shrink improved bits per wafer and module efficiency for in-memory computing, big-data analytics, and general server refresh cycles.

These chips appeared in standard DIMM form factors for data-center and enterprise systems during the 2020–2022 period before 1a and later nodes took over volume production.

LPDDR5 and LPDDR4X Mobile Applications

1z found significant use in low-power mobile DRAM:

• A 16 Gb LPDDR5 die (H58G66AK6H-X132, internal die marking MDHD5E_20104) was extracted from the Apple iPhone 15 Pro. It used the 1z process with the measured 42.0 nm word-line and 47.4 nm bit-line pitches.
• A 12 Gb LPDDR4X 1z die appeared in the Huawei Nova 12 Pro, supporting 4,266 Mbps and delivering roughly 45% power savings on I/O operations versus earlier LPDDR4.

These implementations targeted smartphones, where the combination of density, speed, and reduced power extended battery life and supported higher-resolution displays and on-device processing. The node also appeared in other mid-to-high-end Android devices from various Chinese brands around 2021–2024.

HBM3 for AI and High-Performance Computing

SK Hynix’s first HBM3 products used 1z DRAM dies. A 16 Gb HBM3 die (H5VG7HMD83X020R) was identified inside NVIDIA’s Grace Hopper Superchip (GH100), packaged in 4th-generation HBM3 stacks. Six such 16 GB sub-packages provided over 3 TB/s aggregate bandwidth between the DRAM and GPU die.

This marked SK Hynix’s entry into HBM3 and supported early AI training and HPC systems. Later HBM3E and HBM4 products moved to more advanced nodes (1b/1c), but 1z served as the process foundation for the initial HBM3 ramp.

Broader Application Context

The 1z node therefore spanned three major DRAM segments:

• Server/enterprise: High-density DDR4 modules for data centers.
• Mobile/consumer: LPDDR5 and LPDDR4X in flagship and mid-range smartphones.
• Accelerator/HPC: Early HBM3 stacks for NVIDIA Hopper-class GPUs.

SK Hynix had stated at the 2019 announcement that it would extend 1z to LPDDR5 and HBM3; those plans were realized in the products above. By the mid-2020s the node had become a mature, cost-optimized process used in long-lifecycle or value-oriented applications while leading-edge volume shifted to 1a–1c and specialized HBM variants.

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5) Challenges, Industry Context, and Legacy

The challenges, industry context, and legacy of SK Hynix’s 1z DRAM node reflect the tightening physical and economic constraints of planar 6F² DRAM scaling in the late 2010s, the competitive dynamics among the three major suppliers, and the node’s role as a cost-effective bridge before EUV became standard. This concluding section of the 1z overview examines the technical hurdles that 1z had to overcome, the market environment in which it launched, and its lasting position in SK Hynix’s technology progression.

Technical Challenges at the 1z Generation

By the third-generation 10 nm-class node, traditional shrink methods were delivering diminishing returns. Shrink factors for SK Hynix, Samsung, and Micron had risen above 0.92× at 1z, meaning each new generation produced a smaller percentage reduction in cell size than earlier nodes. Maintaining cell capacitance above the 6–7 fF target required new high-k materials and a shift toward quasi-cylindrical capacitor structures; SK Hynix specifically introduced a previously unused substance to address this.

Other difficulties included:

• Increased parasitic capacitance and resistance in tighter pitches.
• Sensing-margin and row-hammer reliability at smaller feature sizes.
• Process-window control with DUV multi-patterning (SADP and related techniques) instead of EUV.

SK Hynix mitigated these through material innovation, buried-word-line/BCAT refinements, and circuit-design changes rather than immediately adopting expensive EUV tools. The approach succeeded in delivering the advertised 27% productivity and 40% power gains, but it also signaled that further planar scaling would become progressively harder.

Industry Context in 2019–2021

The DRAM market at the time of 1z’s introduction was an oligopoly dominated by Samsung, SK Hynix, and Micron. All three were racing through the 10 nm-class generations (1x → 1y → 1z) on roughly similar cadences, with Samsung often slightly ahead on some products and Micron emphasizing density on others. EUV lithography was still being qualified or used only on selected layers; full EUV insertion began in earnest at the subsequent 1a/1α nodes around 2021.

The period was also cyclically volatile. Memory makers needed to extract more bits per wafer to improve margins during potential oversupply while funding R&D for the next shrinks. SK Hynix’s decision to stay with DUV at 1z provided a cost advantage versus competitors beginning to insert EUV, helping it compete on price-sensitive DDR4 and mobile products.

Demand drivers included server high-density modules, smartphone LPDDR upgrades, and the emerging need for higher-bandwidth memory that would later explode with AI accelerators. 1z arrived just before that AI-driven HBM surge reshaped capacity allocation.

Legacy and Transition

1z served as a practical, high-volume bridge node. It enabled SK Hynix’s first HBM3 products (used in NVIDIA Hopper systems) and supplied 16 Gb LPDDR5/LPDDR4X dies for flagship smartphones. The process demonstrated that meaningful density and efficiency improvements remained possible without EUV, buying time and generating cash flow while the company prepared 1a (first EUV DRAM, ~25% additional chips-per-wafer gain) and later 1b/1c nodes.

By 2026, 1z had become a mature/legacy technology. Key production sites such as the Wuxi fab completed conversion from 1z to 1a. Remaining 1z capacity supported cost-sensitive or long-lifecycle applications. The node’s success contributed to SK Hynix’s later leadership in HBM for AI and its 2024 world-first 1c 16 Gb DDR5 development.

In the broader DRAM roadmap, 1z marked one of the last generations in which DUV multi-patterning alone could still deliver competitive results. Subsequent nodes required more EUV layers, and the industry began evaluating 4F² cells, vertical-channel transistors, and eventual 3D DRAM architectures as planar 6F² scaling approached its limits. SK Hynix’s 1z work therefore stands as a well-executed incremental step that balanced performance, cost, and manufacturability during a transitional phase of DRAM technology.

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