SK Hynix’s 1x(1Xnm or D1x) DRAM Node: The company’s First-Generation 10 nm-Class process Technology

SK Hynix’s 1x DRAM node represents the company’s first-generation 10 nm-class process technology, marking its formal entry into the single-digit-nanometer era of DRAM manufacturing around 2018.

This designation sits at the start of a sequential labeling scheme (1x → 1y → 1z → 1a → 1b → 1c) used across the DRAM industry for successive shrinks within the broad “10 nm-class” (roughly 10–19 nm half-pitch range). The core topic centers on the technical, historical, and competitive significance of this foundational node for SK Hynix, including how it enabled further scaling, productivity gains, and product advancements, while highlighting the physical and process challenges that defined early 10 nm-class DRAM.

Industry Context for 10 nm-Class DRAM Nodes

DRAM manufacturers (SK Hynix, Samsung, and Micron) adopted letter-based naming once feature sizes entered the 10–19 nm regime. “10 nm-class” does not refer to a precise transistor gate length in the logic-foundry sense but primarily to the half-pitch of critical features such as the active area or wordline/bitline in the memory cell array.

  • 1x (or 1X): First generation, typically associated with ~17–19 nm features.
  • Subsequent nodes progressively tightened pitches (1y ~14–16 nm range, 1z ~11–13 nm, then 1a/1b/1c pushing into the low teens and below).
  • Samsung pioneered commercial 10 nm-class DRAM mass production in 2016 using ArF immersion lithography and quadruple patterning (without EUV at the outset). SK Hynix followed into the class in 2018.

This nomenclature reflects the industry’s shift from simple micron-to-nanometer scaling to multi-patterning and, later, EUV lithography as optical limits and cell capacitance challenges intensified.

Timeline and Entry into the 10 nm Class at SK Hynix

SK Hynix’s path to 1x built on earlier milestones: 60 nm-class (2006), 40 nm (2009), 30 nm (2010), and 20 nm-class (around 2012). Company materials explicitly note reaching the 10 nm class in 2018.

By late 2018, SK Hynix announced development of its second-generation 10 nm-class (1Ynm) 8 Gb DDR4 DRAM. Official comparisons stated that the 1Y node delivered approximately 20% higher productivity and more than 15% better energy efficiency versus the prior-generation 1Xnm DRAM. This confirms 1x as the established first-generation baseline by that point. Shipping of 1Y products was planned for early 2019.

The 1x node itself supported high-volume products including DDR4 and LPDDR4/LPDDR4X variants. TechInsights analyses of SK Hynix 1x LPDDR4X devices further document its commercial presence in the late 2010s.

Key Technical Characteristics and Challenges of the 1x Node

DRAM scaling at this stage centered on the classic 1T1C (one-transistor, one-capacitor) cell while fighting several physical limits:

  • Cell size and pitch reduction: Aggressive shrinks in active, wordline, and bitline pitches increased bit density but reduced storage-node capacitance. Maintaining adequate capacitance (typically targeting several fF per cell) required taller or more complex capacitor structures and optimized high-k dielectrics.
  • Lithography: Early 10 nm-class production relied on ArF immersion multi-patterning (double/quadruple patterning) rather than full EUV. EUV adoption came later—partial use on 1y and full production use starting with the 1a node in 2021.
  • Transistor and sensing challenges: Buried wordline (or recessed-channel) cell transistors, sense-amplifier improvements, and leakage control became critical. Higher resistance and variability at smaller dimensions increased the risk of data errors and power overhead.
  • Productivity gains: Each successive node aimed for higher net die count per wafer. Later nodes quantified clear lifts (e.g., ~25% more chips per wafer from 1z to 1a), implying meaningful density and cost benefits already realized at the 1x-to-1y transition.

Compared with contemporaneous Micron and Samsung 1x implementations, differences appeared in active/wordline/bitline pitch prioritization and resulting bit densities, reflecting each company’s cell-design philosophy.

Evolution Beyond 1x and Competitive Positioning

The 1x foundation enabled a clear roadmap:

GenerationApproximate Timing (SK Hynix milestones)Notable Features / Advances
1xEntry ~2018First 10 nm-class; multi-patterning baseline
1yDevelopment announced 2018; shipping ~2019~20% productivity / >15% power gain vs 1x; early DDR5 work
1zDevelopment ~2019Higher density (e.g., 16 Gb DDR4); still largely non-EUV for cost
1aMass production 2021First full EUV volume production; ~25% more dies/wafer vs 1z; LPDDR4
1bMid-2020sFurther density/performance; platform for later nodes
1cDevelopment 2024; volume ramp 2025Sixth-generation; low-10 nm range; EUV + new materials; 11% speed / 9% power gains vs 1b; applications in DDR5, HBM, LPDDR

SK Hynix leveraged the 1x platform for both commodity (DDR4/LPDDR) and emerging high-bandwidth products. By the 1a/1b era the company had introduced EUV more systematically and applied innovations such as High-K Metal Gate (HKMG) first to mobile DRAM, unlocking higher speeds and lower leakage for LPDDR5X/LPDDR5T. The 1c node (announced 2024) continues this trajectory with design-process co-optimization and is positioned for HBM, LPDDR6/7, and GDDR variants.

Competitively, Samsung held an early lead in 10 nm-class volume, while Micron pursued its own 1x–1α sequence with different EUV timing. SK Hynix’s sequential execution and later leadership claims on 1c illustrate sustained process capability.

Broader Implications and Ongoing Challenges

The 1x node demonstrated that classical planar DRAM scaling remained viable into the mid-to-late teens of nanometers, buying time before more radical architectural shifts (e.g., 3D DRAM concepts or vertical transistors) become necessary. However, each generation has faced diminishing returns on pure density: shrink factors have approached or exceeded 0.9, capacitance continues to pressure high-k and structural innovations, and EUV cost/complexity rises.

From a market perspective, 1x-era products supported the transition to higher-capacity modules and mobile packages at a time of rising demand from smartphones, servers, and early AI/HPC workloads. Subsequent nodes have amplified these benefits—higher bandwidth, lower power, and greater bits per wafer—while feeding the explosive growth of HBM for AI accelerators.

In summary, SK Hynix’s 1x DRAM node was the critical first step into the 10 nm-class regime. It established process know-how, multi-patterning competence, and a scalable product platform that successive generations (especially EUV-enabled 1a and beyond) have extended. The node’s legacy is visible in today’s high-performance, power-efficient DRAM that underpins data-center, mobile, and AI systems, even as the industry confronts the physical limits of further planar shrinks.

1) Industry Context for 10 nm-Class DRAM Nodes

The 10 nm-class DRAM nodes represent a pivotal phase in memory semiconductor evolution, spanning roughly the mid-2010s onward. This era marks the transition from relatively straightforward scaling in the 20–30 nm range into a regime of intensifying physical, lithographic, and economic constraints. Unlike logic foundry nodes (where “10 nm” is largely a marketing label disconnected from actual dimensions), DRAM’s 10 nm-class designation more closely tracks the half-pitch of critical cell features—primarily the active area—typically ranging from about 10–19 nm.

Defining the 10 nm-Class and Naming Conventions

DRAM manufacturers (Samsung, SK Hynix, and Micron) adopted a letter-based generational scheme once feature sizes entered the single-digit teens of nanometers. The broad “10 nm-class” umbrella covers multiple successive shrinks:

  • 1x (or 1X / D1x): First generation (~17–19 nm half-pitch range).
  • 1y (1Y / D1y): Second generation (~14–16 nm).
  • 1z (1Z / D1z): Third generation (~11–13 nm).
  • Subsequent nodes: 1a / 1α (alpha), 1b / 1β (beta), 1c / 1γ (gamma), and beyond, progressively tightening dimensions into the low teens and approaching or entering sub-10 nm territory.

Samsung and SK Hynix primarily use Latin letters (1x–1c), while Micron shifted to Greek letters (1α, 1β, 1γ) after exhausting the Roman alphabet. These labels do not correspond to exact transistor gate lengths as in logic processes; they approximate the minimum half-pitch in the memory cell array.

The industry entered this class around 2016, when Samsung became the first to mass-produce 10 nm-class (1x) 8 Gb DDR4 DRAM using ArF immersion lithography and multi-patterning techniques, without relying on extreme ultraviolet (EUV) tools at the outset.

Historical Progression and Competitive Timeline

Prior to the 10 nm class, DRAM scaling followed clearer integer-nanometer steps: 40 nm-class (around 2008–2009), 30 nm-class (~2010–2011), and 20 nm-class (~2012–2015). Productivity gains were substantial—often 20–30% or more dies per wafer per generation—driven by cell shrinks under the dominant 6F² architecture (where F is the minimum feature size).

Key milestones in the 10 nm era include:

  • 2016: Samsung launches the industry’s first 10 nm-class (1x) DRAM, delivering >30% higher wafer productivity and faster data rates versus 20 nm predecessors. Core enablers were proprietary cell design, quadruple patterning technology (QPT), and ultra-thin dielectric deposition for capacitors.
  • ~2017–2018: SK Hynix and Micron enter the class with their own 1x nodes. SK Hynix reached 10 nm-class production in 2018.
  • 2018–2019: 1y nodes ramp; Samsung and others begin limited EUV exploration.
  • 2019–2020: 1z nodes appear (Samsung mass production of 1z DDR4 in 2019); EUV begins limited volume use (Samsung first for DRAM).
  • 2021 onward: 1a / 1α nodes achieve volume production (SK Hynix 1a with full EUV in 2021; Micron 1α shipments). Later generations (1b/1β, 1c/1γ) continue into the mid-2020s, with 1c positioned as the sixth-generation 10 nm-class node.

By the mid-2020s, the three major suppliers control >95% of the global DRAM market. Density scaling has slowed dramatically—from historical ~2× per generation to roughly 10–25% bit-density gains per node—reflecting the physical limits of planar cells.

Core Technical Challenges

Scaling into and through the 10 nm class exposed multiple interrelated barriers:

Lithography and Patterning

Early nodes relied heavily on ArF immersion multi-patterning (double, triple, or quadruple patterning such as LELE or self-aligned techniques). This increased process complexity, cost, and defect risk through pitch walking, overlay errors, and alignment challenges. EUV (13.5 nm wavelength) was gradually introduced to reduce mask counts and improve precision—first partially on 1y/1z, then more extensively from 1a onward. Even with EUV, multi-patterning remains necessary for the tightest features (e.g., capacitor holes), and stochastic defects become significant at smaller pitches.

Cell Capacitance and Structure

The classic 1T1C (one-transistor, one-capacitor) cell requires sufficient capacitance (typically several fF) for reliable charge storage against leakage. As lateral dimensions shrink, capacitors must grow taller (high aspect-ratio structures, often cylindrical or quasi-cylindrical) or use advanced high-k dielectrics. Deposition of defect-free, ultra-thin layers inside deep holes strains process capability. Feature sizes approaching atomic scales introduce variability in electron behavior and signal integrity.

Transistor and Peripheral Challenges

Buried wordline (or recessed-channel) access transistors, sense-amplifier performance, leakage control, and row-hammer mitigation grow harder. Higher resistance and variability demand design-process co-optimization. Later nodes introduced High-K Metal Gate (HKMG) in mobile DRAM to cut leakage while enabling higher speeds.

Economic and Yield Pressures

Each generation delivers smaller density uplifts while process steps and equipment costs (especially EUV scanners) rise. Yield management becomes critical; slower scaling makes greenfield capacity expansion the primary lever for bit growth rather than pure node migration.

Market and Strategic Implications

The 10 nm-class era coincided with explosive demand growth from smartphones (LPDDR), servers/data centers (DDR4/DDR5), graphics (GDDR), and especially AI/HPC workloads via High Bandwidth Memory (HBM). Higher bit densities and power efficiency directly supported larger capacities, lower power, and higher bandwidth at the system level.

However, the slowing of pure dimensional scaling has shifted competitive focus toward:

  • Process maturity and yield leadership.
  • Product differentiation (e.g., HBM stacking, specialized low-power variants).
  • Architectural evolution beyond pure planar 6F² cells—toward 4F² layouts with vertical channel transistors (VCT) for sub-10 nm nodes, and longer-term 3D DRAM stacking analogous to the earlier 3D NAND transition.

Chinese entrants such as CXMT operate several generations behind on advanced nodes, constrained by equipment access, while the big three continue incremental advances within and beyond the 10 nm class.

Looking Ahead

As of the mid-2020s, the industry remains within or just transitioning out of the broader 10 nm-class framework, with 1c/1γ nodes in volume ramp and sub-10 nm explorations (sometimes labeled 10a or similar) underway using 4F² + VCT approaches. High-NA EUV, new materials, and eventual 3D architectures will define the next decade. The 10 nm-class period thus serves as both a technical high-water mark for classical planar scaling and a bridge to more radical memory architectures required by AI-driven bandwidth and capacity demands.

In essence, the industry context of 10 nm-class DRAM nodes is one of diminishing returns on traditional shrinks, rising process complexity, strategic adoption of EUV, and a gradual pivot from pure miniaturization toward architectural innovation—while still delivering the density, performance, and efficiency gains that underpin modern computing systems.

2) Timeline and Entry into the 10 nm Class at SK Hynix

SK Hynix formally entered the 10 nm-class DRAM era in 2018, following earlier progress through the 20 nm range by around 2012. This marked the company’s transition into the first generation (1x) of single-digit-nanometer-class process technology and set the foundation for subsequent generations (1y, 1z, 1a, 1b, and 1c). The progression reflects both competitive catch-up with Samsung (which commercialized the first 10 nm-class DRAM in 2016) and SK Hynix’s own roadmap of incremental shrinks, productivity gains, and later EUV adoption.

Pre-10 nm Foundations

SK Hynix advanced steadily through earlier nodes:

  • 60 nm-class around 2006.
  • 40 nm-class in 2009.
  • 30 nm-class in 2010–2011.
  • 20 nm-class by 2012, including industry-first developments such as 20 nm-class LPDDR4 in late 2013.

These steps built process expertise in multi-patterning, cell design, and high-aspect-ratio capacitors that would prove essential for the tighter pitches of the 10 nm class.

Entry into the 10 nm Class (2018)

Company statements confirm that SK Hynix reached the 10 nm class in 2018. The 1x node served as the first-generation baseline. By November 2018, the company publicly announced development of its second-generation 10 nm-class (1Ynm) 8 Gb DDR4 DRAM. Official comparisons highlighted approximately 20% higher productivity and more than 15% lower power consumption relative to the preceding 1Xnm generation, confirming that 1x production was already established.

Key 2018 milestones included:

  • Development of 1Ynm 8 Gb DDR4 (announced November 2018), with mass production and shipping targeted for the first quarter of 2019.
  • Parallel development of 1Ynm 16 Gb DDR5 (also announced November 2018), which later supported the world’s first commercial DDR5 launch in October 2020.

These products targeted PC, server, and eventually mobile applications, leveraging multi-patterning (primarily ArF immersion) without full EUV reliance at this stage.

Subsequent Generations and Key Milestones

The timeline after initial 10 nm-class entry shows steady progression:

  • 2019: Development of 1Znm 16 Gb DDR4 (announced October 2019). This third-generation node delivered roughly 27% higher productivity versus 1Y and improved power efficiency. Mass-production preparations were targeted for year-end 2019, with shipments in 2020. The node retained cost advantages by largely avoiding expensive EUV.
  • 2020: Commercial launch of the world’s first DDR5 DRAM (based on earlier 1Y development work). HBM2E mass production also ramped, supporting high-bandwidth applications.
  • 2021: Mass production of 1anm (fourth-generation 10 nm-class) 8 Gb LPDDR4 mobile DRAM beginning in July, marking SK Hynix’s first full use of EUV lithography for volume DRAM production (following limited/partial use on prior nodes). The 1a node offered about 25% more chips per wafer versus 1z, along with higher speeds (up to 4266 Mbps) and ~20% lower power. Supply to smartphone makers began in the second half of 2021.
  • Mid-2020s: 1b (fifth-generation) matured as a high-performance platform. In August 2024, SK Hynix announced the world’s first 16 Gb DDR5 on the 1c (sixth-generation) node, with mass-production readiness targeted within 2024 and volume supply from 2025. The 1c process delivered roughly 11% higher speed and 9% better power efficiency versus 1b, while extending the 1b design platform for efficiency.

By late 2025–2026, 1c capacity was ramping significantly (targeting roughly half of DRAM output by end-2026 in some projections), with applications expanding to HBM variants, LPDDR6, and other advanced products. Concurrently, the Wuxi fab completed upgrades from 1z toward higher 1a shares.

Strategic Context of the Entry

SK Hynix’s 2018 entry into the 10 nm class occurred a couple of years after Samsung’s pioneering 1x mass production. The company prioritized rapid successive generations (1x to 1y within the same year of formal class entry) and later leveraged EUV more systematically starting with 1a. This approach supported both commodity DRAM (DDR4/LPDDR) volume and premium segments (DDR5, HBM), while delivering measurable productivity and efficiency gains at each step.

The overall sequence—1x (entry ~2018) → 1y (2018/2019) → 1z (2019/2020) → 1a (2021, EUV volume) → 1b → 1c (2024/2025)—illustrates a consistent cadence of approximately 1–2 years per major generation within the 10 nm-class umbrella. It positioned SK Hynix to compete effectively on density, cost, performance, and technology leadership, particularly as demand shifted toward higher-bandwidth and lower-power memory for data centers, mobile devices, and AI accelerators.

In summary, SK Hynix’s formal entry into the 10 nm class in 2018 with the 1x node, followed by swift advancement to 1y and beyond, established a scalable process platform that has underpinned the company’s DRAM roadmap through the mid-2020s.

3) Key Technical Characteristics and Challenges of the 1x Node

The 1x node (also styled 1Xnm or D1x) was SK Hynix’s first-generation 10 nm-class DRAM process, corresponding to an approximate half-pitch in the 17–19 nm range. It represented the company’s formal entry into the single-digit-nanometer regime around 2018 and served as the baseline against which later generations (1y and beyond) measured productivity, power, and density gains. Like contemporaneous implementations from Samsung and Micron, it retained the industry-standard 6F² cell architecture while pushing the limits of ArF immersion multi-patterning, high-aspect-ratio capacitors, and buried-wordline transistors.

Core Technical Characteristics

Cell Architecture and Dimensions

The 1x node continued the 1T1C (one-transistor, one-capacitor) design with a 6F² layout. Critical pitches—active area, wordline (WL), and bitline (BL)—were tightened relative to prior 20 nm-class (2y/2z) nodes. Industry analyses of peer 1x devices (notably Micron’s, which shared similar active-pitch prioritization with SK Hynix and Samsung) showed active pitches reduced substantially (on the order of 40% in some comparisons versus prior generations), while WL and BL pitches were adjusted to balance density, resistance, and manufacturability.

Bit density improved versus 20 nm-class predecessors, enabling higher net dies per wafer. Exact SK Hynix 1x cell sizes were not publicly disclosed in the same detail as later nodes, but the generation delivered the foundational density uplift that subsequent 1y announcements quantified at roughly 20% higher productivity.

Lithography and Patterning

Production relied primarily on 193 nm ArF immersion lithography combined with multi-patterning techniques (double, triple, or quadruple patterning such as LELE or self-aligned variants). Full EUV was not yet in volume use; SK Hynix later introduced partial EUV on 1y and full production EUV starting with the 1a node in 2021. This multi-patterning approach enabled the required feature sizes without waiting for EUV tool maturity or cost reduction.

Transistor and Capacitor Structure

  • Access transistors typically used buried wordline (bWL) or recessed-channel architectures to improve short-channel control and reduce leakage at smaller dimensions.
  • Capacitors were high-aspect-ratio cylindrical (or evolving toward quasi-cylindrical) structures with high-k dielectrics to maintain adequate storage capacitance (targeting several fF per cell) despite reduced lateral footprint.
  • Sense-amplifier and peripheral circuit optimizations addressed increased resistance and variability.

Performance and Product Attributes

1x-based products supported standard DDR4 and LPDDR4/LPDDR4X interfaces with competitive data rates for the era. Later official comparisons (when announcing 1y) indicated the 1x baseline already provided solid energy efficiency that subsequent nodes improved upon by more than 15%.

Primary Technical Challenges

Capacitance Retention

As cell area shrank, maintaining sufficient capacitance became the central physical constraint. Reduced lateral dimensions required taller capacitors with extreme aspect ratios, complicating etch uniformity, sidewall coverage for high-k films, and defect control. Insufficient capacitance directly threatened data retention, sensing margins, and refresh rates. This challenge intensified across the entire 10 nm-class era and remains a limiting factor even in later nodes.

Multi-Patterning Complexity and Yield

Achieving 1x pitches with ArF immersion demanded multiple exposure and etch steps. This introduced risks of pitch walking, overlay errors, critical-dimension (CD) variation, and higher defect densities. Process control, mask alignment, and cost all rose sharply. Industry commentary from the period noted that patterning 1x nm half-pitches and contacts without EUV required “long and tedious work” to hold CD uniformity and alignment quality.

Transistor Reliability and Leakage

Smaller channel lengths and higher electric fields increased leakage currents and short-channel effects. Buried-wordline structures helped, but variability in threshold voltage, contact resistance, and row-hammer susceptibility required careful process and design co-optimization. Sense-amplifier performance also became more critical as signal margins tightened.

Interconnect and Parasitic Effects

Higher resistance in narrower wordlines and bitlines, combined with increased parasitic capacitance, impacted speed and power. Signal integrity and noise immunity demanded refined circuit design and materials.

Economic and Manufacturing Trade-offs

While multi-patterning avoided the high capital cost of early EUV tools, it raised mask counts, process steps, and cycle time. Yield learning curves were steeper than in prior nodes, and the density gains, while meaningful, were smaller in relative terms than historical generational jumps.

Comparative Context and Legacy

Peer analyses (e.g., TechInsights examinations of Micron 1x devices) showed that SK Hynix and Samsung generally prioritized the smallest active pitches, whereas some earlier Micron approaches had emphasized wordline pitch. Samsung’s 1x achieved higher reported bit densities in some product comparisons, reflecting differences in cell layout efficiency and process maturity.

The 1x node successfully demonstrated that classical planar 6F² DRAM could extend into the mid-to-late teens of nanometers using existing lithography infrastructure. It provided the process platform, learning, and product volume that enabled rapid follow-on generations (1y announced the same year as formal 10 nm-class entry). Many of the challenges first encountered at 1x—capacitance scaling, multi-patterning burden, and variability—became more acute in later nodes and ultimately drove wider EUV adoption, high-k/metal-gate innovations, and exploration of 4F² or vertical architectures beyond the pure 10 nm-class regime.

In short, the 1x node was characterized by aggressive pitch reduction under a multi-patterning regime, high-aspect-ratio capacitors, and buried-wordline transistors, while its principal challenges centered on preserving cell capacitance, controlling multi-patterning defects and variability, and managing the rising cost and complexity of further planar shrinks. These traits defined both its technical success as SK Hynix’s entry point into the 10 nm class and the roadmap pressures that shaped every subsequent generation.

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