Samsung’s 1z (D1z) DRAM node: The company’s third-generation 10 nm-class process technology

Samsung’s 1z (D1z / third-generation 10 nm-class) DRAM technology represents a pivotal step in the company’s DRAM scaling roadmap. It is the third generation within the broader 10 nm-class process family (following 1x and 1y), delivering higher bit density, improved manufacturing productivity, better power efficiency, and the first commercial use of extreme ultraviolet (EUV) lithography in high-volume DRAM production.

Historical Context and Naming Convention

DRAM process nodes are labeled by generation rather than a precise half-pitch dimension because manufacturers have long avoided disclosing exact feature sizes. The industry convention for the 10 nm-class era runs:

1x (first generation, roughly mid-to-late teens of nm)
1y (second generation)
1z / D1z (third generation)
later nodes: 1a, 1b, 1c, 1d, and beyond

Samsung announced development of its 1z-nm 8 Gb DDR4 in March 2019 and targeted mass production in the second half of that year. The node was positioned as the industry’s then-smallest memory process. Independent analysis later measured the design rule (D/R) at approximately 15.7 nm, confirming it as a meaningful shrink from the prior 1y generation (around 17.1 nm).

Key Technical Characteristics

Design rule and cell metrics TechInsights measurements on production LPDDR5 devices showed:

Design rule reduced from ~17.1 nm (1y) to 15.7 nm (1z)
Cell size reduced to ~0.00197 µm²
Bit density reaching ~0.261–0.273 Gb/mm² depending on die capacity (12 Gb or 16 Gb examples)
Die size reductions of roughly 15–20 % versus comparable 1y parts, translating into >15–20 % higher manufacturing productivity (more chips per wafer)

Lithography strategy

Samsung initially developed 1z using argon-fluoride immersion (ArF-i) multi-patterning and later introduced limited EUV for selected layers, most notably the bit-line pad (BLP) / storage-node landing pad. This hybrid approach reduced multi-patterning complexity and cost while improving pattern fidelity. Some 12 Gb LPDDR5 dies used EUV on the BLP layer; certain 16 Gb variants remained non-EUV. This made Samsung the first DRAM maker to apply EUV in high-volume production.

Process and architecture highlights

Continued use of the traditional 6F² cell architecture with buried word-line (BCAT) transistors
Capacitor process refinements (quasi-cylindrical structures and optimized high-k dielectrics) to maintain adequate capacitance as cell size shrank
Focus on peripheral circuit improvements for higher data rates and lower power

These changes enabled higher-capacity monolithic dies and thinner packages, critical for mobile and high-end computing applications.

Products and Applications

Samsung leveraged 1z across multiple product families:

DDR4: 8 Gb devices for servers and high-end PCs (mass production from late 2019 into 2020)
LPDDR5: Industry-first 16 Gb LPDDR5 chips and 16 GB packages announced for mass production in August 2020. These offered 6,400 Mb/s data rates (16 % faster than prior 12 Gb LPDDR5 solutions at 5,500 Mb/s) and packages ~30 % thinner than predecessors. Only eight 16 Gb chips were needed for a 16 GB module, versus more dies in earlier mixed-capacity packages.
Deployment in flagship smartphones such as the Galaxy S21 series (2021)
Extension into graphics (GDDR6), automotive, and enterprise server modules

The technology also supported the broader industry transition toward DDR5, LPDDR5, and higher-bandwidth interfaces by providing a denser, more efficient foundation.

Competitive Landscape

All three major DRAM suppliers—Samsung, SK Hynix, and Micron—brought 1z-class products to market around the same period. Comparisons from independent analyses showed:

Samsung often led in bit density on mobile LPDDR5 dies and was first with limited EUV
Micron emphasized strong density and power efficiency on certain DDR4 and LPDDR4X parts without EUV
SK Hynix achieved high bit densities on some 16 Gb DDR4 devices

Samsung’s early 1z introduction and EUV adoption helped maintain process leadership and cost advantages at a time when scaling was becoming progressively harder due to physical limits on cell capacitance, leakage, and patterning complexity.

Challenges and Industry Significance

By the 1z generation, DRAM scaling was already approaching practical limits of the planar 6F² architecture. Cell capacitance continued to decline (approaching or falling below 10 fF/cell in later analyses of D1z-class devices), requiring ever-more sophisticated capacitor engineering and sensing techniques. Shrink factors between successive generations rose above 0.9, indicating diminishing returns.

1z therefore served as both a commercial success and a bridge node. It delivered tangible density and cost benefits while Samsung and peers prepared more aggressive EUV adoption, high-k metal-gate peripherals, and eventually new cell architectures (including 4F² and vertical-channel transistors) for sub-10 nm nodes.

Legacy and Later Generations

Subsequent Samsung nodes (1a, 1b, 1c, and beyond) built directly on 1z learnings, expanding EUV layers and refining materials. The 1z generation remains a clear milestone: the first widespread third-generation 10 nm-class DRAM, the commercial debut of EUV in DRAM manufacturing, and a key enabler of higher-capacity, higher-speed, lower-power memory that powered the early 5G smartphone and server boom of 2020–2022.

In summary, Samsung’s 1z (D1z) technology exemplifies the incremental yet essential engineering progress that has sustained DRAM density scaling for decades—combining process innovation, selective adoption of new lithography tools, and careful productization across mobile, server, and graphics markets.

1) EUV lithography in DRAM manufacturing

EUV lithography in DRAM manufacturing refers to the application of extreme ultraviolet (EUV) light sources—operating at a 13.5 nm wavelength—to pattern critical layers in dynamic random-access memory chips. This technology has become essential for continuing density scaling in the 10 nm-class and beyond, where traditional deep ultraviolet (DUV) multi-patterning grows increasingly complex and costly.

Fundamentals of EUV Lithography

EUV systems, primarily supplied by ASML, generate light at 13.5 nm (far shorter than the 193 nm ArF immersion DUV wavelength). This enables finer resolution with fewer patterning steps.

Key advantages over pure DUV multi-patterning include:

Single-exposure patterning for aggressive pitches that previously required self-aligned double/quadruple patterning (SADP/SAQP) or litho-etch-litho-etch (LELE) sequences.
Improved pattern fidelity and reduced process complexity, lowering the total number of masks and process steps.
Better critical-dimension control in high-density cell-array features such as bit-line pads, storage-node landing pads, word lines, and active-area cuts.

In DRAM, EUV is typically applied selectively to only a few critical layers (often 1–6 depending on the node), rather than the 20+ layers common in advanced logic processes. This selective use improves tool productivity per wafer while still delivering meaningful density and cost benefits.

Adoption Timeline by Major Manufacturers

Samsung led the industry in applying EUV to high-volume DRAM production:

Samsung: First commercial use on the 1z (third-generation 10 nm-class) node around 2020, initially limited to one layer (primarily the bit-line pad / storage-node landing pad). Layer count expanded progressively; later nodes such as 1c use five or more EUV layers.
SK Hynix: Introduced EUV in mass production with the 1a (fourth-generation 10 nm-class) node in 2021, starting with one layer and expanding thereafter. By the 1c generation, reports indicate five or more (up to six) EUV layers. In 2025, SK Hynix installed the industry’s first production-oriented High-NA EUV system (ASML Twinscan EXE:5200B / NXE:5200B class) at its M16 fab for development and future mass production.
Micron: The last of the three major suppliers to adopt EUV at scale. It relied on advanced DUV multi-patterning through 1α and 1β nodes, then introduced EUV for pilot production on the 1γ (1-gamma / equivalent to 1c) node, targeting high-volume manufacturing from 2025.

Chinese producers such as CXMT have lagged due to export controls restricting access to EUV tools.

Technical Benefits and Process Integration

EUV addresses several scaling bottlenecks inherent to planar 6F² DRAM cells:

Density and productivity gains: Reduces multi-patterning steps, enabling higher bit density and more dies per wafer. Samsung reported >15–20 % productivity improvements when moving from 1y to 1z with limited EUV.
Pattern quality: Mitigates some overlay and edge-placement errors associated with multi-patterning. Stochastic effects (random photon shot noise and resist variation) remain a challenge and require specialized resists, etch processes, and metrology.
Cost dynamics: Although each EUV scanner costs roughly $150–250 million (Low-NA) or significantly more for High-NA (~$350–450 million), the reduction in total process steps and improved yields can lower cost per bit at advanced nodes.
Complementary techniques: Often combined with advanced photoresists (including metal-oxide resists), phase-shift masks, and optimized etch tools that correct EUV-specific line-edge roughness.

High-NA EUV (numerical aperture of 0.55 versus 0.33 for Low-NA) further improves resolution to approximately 8 nm, enabling single-exposure patterning of features previously requiring multi-patterning and supporting denser cell arrays or combined critical layers (for example, bit-line periphery and hexagonal storage-node pillars).

Challenges and Limitations

Adoption is not without hurdles:

Stochastic defects and yield: EUV photons are fewer at a given dose, increasing random variation that can affect line-edge roughness and contact-hole uniformity.
Capital intensity: Tools are extremely expensive; DRAM fabs typically install fewer scanners than logic fabs because fewer layers use EUV.
Resist and mask infrastructure: Specialized EUV photoresists, pellicles, and mask blanks are required; new absorber materials continue to be developed for higher throughput.
Architectural shifts: As the industry moves toward 4F² cells, vertical-channel transistors, and eventual 3D DRAM, the relative value of High-NA EUV may change. Some analyses suggest 3D DRAM architectures could reduce reliance on the most aggressive EUV layers by relaxing lateral dimensions.

Industry Impact and Future Outlook

EUV has become a defining technology for leading-edge DRAM (1a/1α and beyond), enabling continued scaling of DDR5, LPDDR5X, GDDR, and especially high-bandwidth memory (HBM) required for AI accelerators. Demand from AI-driven HBM production has significantly increased EUV tool orders from memory makers, contributing to strong growth for ASML.

Looking ahead:

Low-NA EUV layer counts are expected to rise further on 1c/1γ and 1d nodes.
High-NA EUV is entering development and early production use, with SK Hynix taking an early lead for DRAM. Full high-volume deployment for memory is projected later in the decade, potentially coinciding with sub-10 nm or early 3D DRAM transitions.
Alternative or complementary approaches (advanced DUV multi-patterning, new materials, and architectural innovation) will continue in parallel, especially for cost-sensitive or specialty memory.

In essence, EUV lithography has transitioned from a logic-centric technology to a core enabler of modern DRAM manufacturing. It allows the industry to push planar scaling further while preparing the process foundation for the next architectural generations of memory.

2) Historical Context and Naming Convention of DRAM Process Nodes

The naming system used for DRAM manufacturing technology—particularly the “10 nm-class” designations such as 1x, 1y, 1z, 1a, and beyond—emerged from practical necessity as traditional numeric process-node labels lost precision and competitive sensitivity. Unlike logic semiconductor nodes (where names like “7 nm” or “5 nm” have long been pure marketing constructs with little direct relation to actual feature sizes), DRAM node names retain a closer, though still approximate, connection to physical dimensions.

Evolution of DRAM Process Naming

For decades, DRAM process technology followed a relatively straightforward numeric progression tied to the half-pitch of the active area in the memory cell array (the distance between adjacent cell transistors, divided by two). Examples include:

40 nm-class (late 2000s)
30 nm-class (around 2010)
20 nm-class (introduced around 2014 by Samsung and peers)

By the mid-2010s, as feature sizes approached the mid-to-low teens of nanometers, manufacturers faced two problems:

Exact half-pitch measurements had become commercially sensitive competitive information.
Incremental shrinks were becoming smaller and harder to distinguish with simple integer labels.

In response, the industry shifted to a letter-based system within broader “class” categories. Samsung’s mass production of the industry’s first 10 nm-class DRAM (8 Gb DDR4) in early 2016 marked the formal start of this era.

The 10 nm-Class Naming System

The overarching “10 nm-class” label covers devices with active-area half-pitches roughly in the 10–19 nm range. Within this class, successive generations are denoted by letters:

Generation	Common Designation	Approximate Half-Pitch Range	Typical Introduction Period	Notes
1st	1x / D1x	~17–19 nm	2016	First 10 nm-class node; Samsung pioneered commercial production
2nd	1y / D1y	~14–16 nm	2017–2018	Continued ArF immersion multi-patterning
3rd	1z / D1z	~11–15 nm (measured ~15.7 nm for Samsung)	2019–2020	First limited EUV adoption by Samsung
4th	1a / D1a / 1α	~12–14 nm range	2020–2021	Broader EUV use
5th	1b / D1b / 1β	~11–13 nm	~2022–2023	Further density gains
6th	1c / D1c / 1γ	~10–12 nm	2024–2025	Leading-edge production nodes
Later	1d / D1d, etc.	Approaching or below 10 nm	Mid-to-late 2020s	Transition toward new architectures

Key points on nomenclature:

Samsung and SK Hynix predominantly use Latin letters (1x, 1y, 1z, 1a, 1b, 1c…).
Micron switched to Greek letters after exhausting the Roman alphabet (1α / 1-alpha, 1β / 1-beta, 1γ / 1-gamma). Thus Micron’s 1γ is roughly equivalent to Samsung/SK Hynix’s 1c.
Some companies prefix “D” (D1x, D1z) to emphasize the DRAM context or internal process codes.
Exact half-pitch values are rarely disclosed officially; independent analysts (e.g., TechInsights) provide measured estimates based on reverse engineering.

This system allows manufacturers to signal generational progress without revealing precise geometries that competitors could exploit.

Why the Shift Occurred

Three interrelated factors drove the change:

Physical scaling limits: Continuing to shrink the traditional 6F² cell while maintaining adequate capacitor capacitance and sensing margin became progressively harder. Shrink factors between generations rose toward 0.9 or higher, reducing the payoff of each step.
Competitive dynamics: Publishing exact nanometer figures invited direct comparisons and potential intellectual-property scrutiny. Letter-based labels provided ambiguity while still communicating relative advancement.
Lithography transition: The move from pure ArF immersion multi-patterning to selective EUV (beginning with Samsung’s 1z) further justified a new naming framework that highlighted process sophistication rather than a single linear dimension.

Broader Historical Perspective

DRAM scaling has always lagged logic in absolute feature size because of the unique requirements of the one-transistor, one-capacitor (1T1C) cell—particularly the need to store sufficient charge in a shrinking volume. From the 1970s through the early 2000s, node names closely tracked gate length or metal half-pitch. After the industry entered the sub-30 nm regime, the divergence between marketed node names and actual critical dimensions accelerated, culminating in the current letter-based 10 nm-class system.

Looking forward, as the industry approaches the practical limits of planar 6F² cells (projected near or below 10 nm), naming conventions may evolve again. Future nodes are expected to incorporate 4F² layouts, vertical-channel transistors, and eventually true 3D DRAM architectures. These shifts could prompt yet another revision of how process generations are labeled—potentially moving away from pure half-pitch references toward architectural descriptors.

In short, the historical context of DRAM naming reflects both the technical realities of memory scaling and the commercial need for strategic ambiguity. The 1x–1z–1a sequence remains the clearest public language the industry has developed for communicating progress within the long-running 10 nm-class era.

3) Design Rule and Cell Metrics in DRAM Technology

In DRAM manufacturing, design rule (D/R) and cell metrics form the quantitative foundation for evaluating process advances, density gains, and competitive positioning. These parameters directly influence bit density, die size, manufacturing productivity (net dies per wafer), power efficiency, and overall cost per bit. For Samsung’s 1z (D1z) generation—the third within the 10 nm-class—and its peers, independent analyses (primarily from TechInsights) provide measured values that reveal both progress and the increasing difficulty of continued scaling.

Core Definitions

Design rule (D/R): Typically the minimum feature size or half-pitch of the active area (the region containing the cell-select transistors) in the memory array. It is the primary metric used to define a DRAM process node.
Cell size: The physical area occupied by one memory cell (1 transistor + 1 capacitor), expressed in µm². For the long-dominant 6F² architecture, cell size ≈ 6 × F², where F is the design-rule feature size.
Bit density: Die capacity (in Gb) divided by die area (in mm²), expressed in Gb/mm². This is the most practical indicator of manufacturing efficiency.
Related pitches: Active (Act), word-line (WL), and bit-line (BL) pitches, which determine cell aspect ratio and array efficiency.

Samsung 1z (D1z) Metrics

TechInsights measurements on production LPDDR5 devices show clear improvements from the prior 1y generation:

Metric	Samsung D1y (12 Gb LPDDR5)	Samsung D1z (12 Gb LPDDR5)	Samsung D1z (16 Gb LPDDR5)	Change (D1y → D1z)
Design rule (D/R)	17.1 nm	15.7 nm	15.7 nm	~8.2% shrink
Cell size	0.00231 µm²	0.00197 µm²	0.00197 µm²	~15% smaller
Die size	53.53 mm²	43.98 mm²	61.20 mm²	~18% smaller (for 12 Gb)
Bit density	0.224 Gb/mm²	0.273 Gb/mm²	0.261 Gb/mm²	~22% higher (12 Gb)

Samsung’s 1z design rule of 15.7 nm and cell size of 0.00197 µm² represented the leading edge at the time of introduction. The smaller die size for the 12 Gb part translated into more than 15% higher manufacturing productivity versus the equivalent 1y device.

Competitive Comparison at the 1z Generation

Cross-vendor data for contemporaneous D1z-class products highlight close competition:

Vendor / Product	Capacity	Design Rule	Cell Size	Bit Density	Notes
Samsung D1z LPDDR5	12 Gb	15.7 nm	0.00197 µm²	0.273 Gb/mm²	EUV on BLP layer in some variants
Samsung D1z LPDDR5	16 Gb	15.7 nm	0.00197 µm²	0.261 Gb/mm²	Non-EUV variant also observed
Micron D1z LPDDR4 / DDR4	16 Gb	15.9 nm	0.00204 µm²	0.234–0.247 Gb/mm²	Pure ArF immersion multi-patterning
SK Hynix D1z DDR4	16 Gb	~15–16 nm range	~0.0020 µm²	Up to 0.296 Gb/mm²	Highest reported bit density among early 1z DDR4 parts

Samsung held a slight edge in cell size and design rule over Micron’s contemporary D1z, while SK Hynix achieved notably high bit density on certain 16 Gb DDR4 dies through optimized layout and process integration.

Scaling Trends and Challenges

Across the industry, the shrink factor (ratio of successive design rules) has risen steadily:

Earlier nodes (pre-1z) often achieved shrink factors of 0.75–0.85.
At the 1z generation, shrink factors exceeded 0.92 for Samsung, SK Hynix, and Micron.
This indicates diminishing returns: each successive generation delivers progressively smaller relative density gains while process complexity and cost rise.

Cell capacitance has also declined, with D1z- and D1a-class devices frequently falling below 10 fF per cell. Manufacturers compensated through quasi-cylindrical capacitor structures, thinner high-k dielectrics (down to ~6–7 nm), and materials engineering, but the trend underscores the physical limits of the planar 6F² architecture.

Later nodes illustrate continued progress. By the D1b / 1β generation, cell sizes had fallen further to approximately 0.00123–0.00133 µm², with feature sizes around 12.5–13.1 nm and bit densities exceeding 0.43 Gb/mm² on advanced mobile and server dies.

Practical Implications

Manufacturing productivity: Smaller cell size and design rule directly increase the number of dies per 300 mm wafer, lowering cost per bit when yields are maintained.
Package and system impact: Higher bit density enables thinner multi-chip packages (critical for mobile devices) and higher-capacity modules for servers and HBM stacks.
Performance and power: Tighter pitches can reduce parasitic capacitance and resistance, supporting higher data rates and lower operating voltages, provided sensing margins remain adequate.
Limits of 6F²: Industry analyses suggest that 10 nm (or slightly below) may represent the practical endpoint for conventional 6F² cells. Beyond this point, transitions to 4F² layouts, vertical-channel transistors, or true 3D DRAM architectures become necessary to sustain density growth.

In summary, design rule and cell metrics at the 1z node demonstrated meaningful but hard-won advances—roughly 8% D/R shrink and 15% cell-size reduction for Samsung relative to 1y—while highlighting the approaching physical and economic boundaries of planar DRAM scaling. These numbers remain the primary language through which process engineers, analysts, and competitors evaluate progress in the memory industry.

4) Lithography Strategy in Samsung’s 1z (D1z) DRAM and the Broader Industry Context

Lithography strategy is one of the most decisive factors in DRAM process technology. It determines how critical layers—especially those in the cell array and near-array periphery—are patterned at ever-smaller dimensions while balancing cost, yield, cycle time, and defectivity. For Samsung’s third-generation 10 nm-class (1z / D1z) node, the approach marked a carefully managed transition from pure ArF immersion multi-patterning toward selective use of extreme ultraviolet (EUV) lithography.

Samsung’s 1z Lithography Approach

Samsung developed and initially produced 1z DRAM using two parallel flows:

ArF immersion (ArF-i) multi-patterning as the baseline for most layers.
Limited EUV applied selectively to one critical mask layer: the storage-node landing pad (SNLP) on the cell array and the bit-line pad (BLP) on the sense-amplifier (S/A) region.

Key measured details from TechInsights analyses of production devices include:

EUV was used on a single mask for the SNLP/BLP layer.
Critical dimension (CD) / pitch for this layer was approximately 40 nm.
BLP line width in the S/A area measured about 13.5 nm.
EUV versions showed improved line-edge roughness (LER) and reduced risk of bridge/short defects compared with pure ArF-i versions of the same layer.

Samsung initially qualified both ArF-i-only and EUV-assisted 1z flows. Early 12 Gb LPDDR5 dies (e.g., markings associated with K4L2E165YC) used EUV on the BLP/SNLP, while some 16 Gb LPDDR5 dies (e.g., K4L6E165YB) remained non-EUV. Over time, production converged toward EUV on that critical layer for high-volume LPDDR5 products. Mass production of 1z began in the second half of 2019, with EUV insertion ramping shortly thereafter (sources indicated a planned switch in late 2019).

This single-layer EUV strategy allowed Samsung to:

Reduce the number of multi-patterning steps (and associated masks/process complexity) for a high-difficulty layer.
Improve pattern fidelity without committing the entire process to expensive EUV tools.
Hedge risk by maintaining a pure ArF-i fallback path during early ramp.

Strategic Rationale

At the 1z node, pure DUV multi-patterning (SADP, SAQP, LELE, etc.) remained technically feasible but was becoming increasingly burdensome. Each additional patterning step raised cost, cycle time, overlay challenges, and defect opportunities. By inserting EUV on just the most critical pad layer, Samsung achieved:

Better local critical-dimension uniformity and lower LER.
Potential reduction in total process steps and cost per wafer once EUV throughput and yield matured.
Early learning on EUV process integration (resist, etch, metrology, mask infrastructure) that would be essential for later nodes.

Samsung had previously demonstrated limited EUV capability on 1x-class sample modules in late 2019; 1z represented the first true high-volume DRAM application.

Competitive Landscape at the Time

Samsung: First mover on EUV in DRAM volume production (1 layer at 1z).
SK Hynix: Introduced EUV later, starting with one layer on the 1a node (2021).
Micron: Continued with pure ArF immersion multi-patterning through 1z and even into 1α / 1β, delaying broad EUV adoption until the 1γ (1c-equivalent) generation around 2025. Micron’s strategy prioritized maximizing the maturity and cost-effectiveness of existing DUV tools for as long as possible.

Evolution Beyond 1z

Samsung’s roadmap called for progressive expansion of EUV layers:

1a: approximately four EUV layers
1b and later: five or more layers

By the 1c generation, industry reports indicated Samsung and SK Hynix targeting five-plus EUV layers, while Micron remained more conservative (often one layer even on early 1c prototypes). The long-term trajectory includes High-NA EUV (0.55 NA) for single-exposure patterning of the most aggressive pitches, although full high-volume DRAM adoption of High-NA remains cautious due to tool cost and the eventual shift toward 4F² or 3D architectures that may relax some lateral scaling pressure.

Key Trade-offs in DRAM Lithography Strategy

Aspect	Pure ArF-i Multi-Patterning	Selective EUV (1z-style)	Broader EUV Adoption (later nodes)
Tool cost	Lower	Moderate (few layers)	High
Process complexity	High (many steps)	Reduced for critical layers	Lower overall for critical features
Pattern fidelity / LER	Good but degrading with more steps	Improved on EUV layers	Significantly better
Cycle time / productivity	Longer due to multi-patterning	Improved once EUV mature	Best potential
Risk / learning curve	Mature	Moderate (early EUV learning)	Higher (stochastic effects, resists, etc.)

In summary, Samsung’s 1z lithography strategy was a pragmatic hybrid: retain mature ArF immersion multi-patterning for the majority of layers while introducing EUV on the single most challenging pad layer. This approach delivered measurable improvements in pattern quality and set the foundation for the multi-layer EUV flows that define later 10 nm-class and sub-10 nm DRAM nodes. It exemplifies the industry’s gradual, risk-managed transition from DUV-centric to EUV-enabled manufacturing.

5) Process and Architecture Highlights of Samsung’s 1z (D1z) DRAM

Samsung’s 1z (D1z) process continued the industry-standard planar 6F² cell architecture while introducing targeted refinements in transistor structure, capacitor integration, and peripheral circuitry. These changes enabled the measured design-rule shrink to ~15.7 nm, cell-size reduction to ~0.00197 µm², and higher bit density relative to the prior 1y generation, all while maintaining manufacturable yields and performance.

Cell Architecture Foundation

The core remains the classic 1T1C (one-transistor, one-capacitor) cell in a 6F² layout. In this arrangement:

The cell occupies a rectangular area of approximately 3F × 2F.
Active areas are arranged in a staggered or honeycomb-like pattern to optimize packing.
Capacitors sit above the bit lines in a capacitor-over-bitline (COB) configuration, the dominant industry approach for density and process compatibility.

This architecture had been the mainstream choice across Samsung, SK Hynix, and Micron for many generations and continued through 1z and several subsequent nodes.

Access Transistor: Buried Channel Array Transistor (BCAT)

Samsung employed a buried word-line (BCAT) structure for the cell-select transistor:

The word line is recessed into the silicon substrate, creating a recessed or saddle-fin channel.
This design shortens the effective channel length while controlling short-channel effects and leakage better than earlier planar transistors.
Metal-gate materials (often involving tungsten or titanium-nitride stacks) were used to optimize work function and reduce resistance.
The buried structure frees surface area for denser capacitor placement and improves array efficiency.

BCAT (or closely related recessed-channel variants) had become the industry standard by the 20 nm and early 10 nm-class nodes; 1z refined the geometry, doping, and gate-stack engineering for the tighter pitches.

Capacitor Structure and Dielectrics

Maintaining adequate cell capacitance (ideally above ~10 fF, though values continued to decline) is one of the hardest challenges at advanced nodes. Samsung’s 1z approach included:

Transition toward quasi-cylindrical capacitor structures (also observed in SK Hynix D1y/D1z devices). These offer better mechanical stability and surface-area utilization than pure cylindrical designs as aspect ratios increase.
High-k dielectric stacks based on zirconium oxide (ZrO₂) or related multi-layer films (e.g., ZrO/AlZrO or optimized variants), with electrical oxide thickness (EOT) pushed lower.
Continued use of metal-insulator-metal (MIM) construction with careful control of dielectric uniformity to minimize leakage while maximizing capacitance.
Storage-node landing pad (SNLP) and plug engineering to ensure reliable contact between the access transistor and the bottom electrode of the capacitor.

These refinements helped offset the natural drop in capacitance that accompanies smaller cell footprints.

Additional Process Features

Bit-line air-gap spacers: Air gaps reduce parasitic capacitance between adjacent bit lines, improving sensing margin and speed.
Peripheral circuit enhancements: Improvements in sense-amplifier design, compensation schemes, and interconnect (including selective use of advanced metals) supported higher data rates and lower power—critical for LPDDR5 and DDR4 products built on 1z.
Stacked DRAM CMOS process: The overall integration remained a stacked approach with the cell array and peripheral transistors fabricated on the same wafer, using multiple metal layers for routing.

Integration and Manufacturing Context

1z devices were produced primarily at Samsung’s advanced Pyeongtaek campus (second production line noted in analyses). The process retained compatibility with existing ArF immersion tools for most layers while inserting limited EUV on the critical SNLP/BLP mask, as detailed in the lithography strategy. This hybrid approach minimized disruption to the mature process flow while delivering the required density gains.

Limitations and Forward Path

Even with these optimizations, cell capacitance continued its long-term decline (D1z and subsequent D1a devices often measured below 10 fF/cell). Shrink factors between generations rose above 0.9, signaling that pure geometric scaling of the 6F² BCAT + COB stack was approaching practical limits. Later nodes therefore expanded EUV layer counts, introduced further gate-stack and dielectric innovations, and ultimately prepared the ground for 4F² layouts, vertical-channel transistors, and 3D DRAM architectures.

In summary, Samsung’s 1z process and architecture highlights represent evolutionary rather than revolutionary advances: refined BCAT transistors, quasi-cylindrical high-k capacitors, air-gap bit-line isolation, and careful peripheral optimization—all built on the proven 6F² COB foundation. These changes delivered the measured density and productivity improvements that made 1z a commercially successful bridge node between the pure multi-patterning era and the multi-layer EUV era of DRAM manufacturing.

6) Products and Applications of Samsung’s 1z (D1z) DRAM Technology

Samsung leveraged its third-generation 10 nm-class (1z / D1z) process across multiple product families, enabling higher density, improved power efficiency, and thinner packages. The technology supported both mainstream computing memory and specialized high-bandwidth or low-power variants, with commercial ramp beginning in the second half of 2019 and expanding significantly in 2020–2021.

Key Product Families

LPDDR5 Mobile DRAM

This was the highest-profile application of the 1z node.

Industry-first 16 Gb LPDDR5 chips mass-produced using the 1z process with limited EUV (announced August 2020).
Data rate of 6,400 Mb/s — approximately 16% faster than prior 12 Gb LPDDR5 devices running at 5,500 Mb/s.
Enabled 16 GB packages using only eight 16 Gb chips (versus more complex multi-die combinations on earlier nodes).
Package thickness reduced by about 30% compared with previous-generation solutions, aiding slim smartphone and foldable designs.
12 Gb LPDDR5 variants were also produced on 1z and appeared in flagship devices.

These chips powered premium smartphones, most notably Samsung’s own Galaxy S21 series (S21, S21+, and S21 Ultra) launched in early 2021. TechInsights confirmed both 12 Gb and 16 Gb 1z LPDDR5 dies in those models. The technology also appeared in other Android flagships and mid-to-high-end devices from Chinese OEMs during the same period.

DDR4 for Servers and PCs

8 Gb DDR4 devices were among the first 1z products announced (development completed March 2019; mass production targeted for the second half of 2019).
Targeted next-generation enterprise servers and high-end PCs expected in 2020.
Offered more than 20% higher manufacturing productivity versus the prior 1y-nm 8 Gb DDR4.
Modules based on these chips supported standard server and desktop form factors (RDIMMs, UDIMMs, SODIMMs).

GDDR6 Graphics Memory

Samsung produced GDDR6 devices on the 1z process (examples analyzed by TechInsights include 8 Gb dies). These targeted high-performance graphics cards, gaming systems, and early AI/accelerated computing platforms that required high bandwidth.

Other and Emerging Uses

Automotive-grade variants with extended temperature ranges were planned or introduced to meet reliability requirements for infotainment, ADAS, and related systems.
The density and power advantages of 1z also supported multi-chip packages (MCPs) and ultra-thin packages suitable for wearables and other space-constrained devices. Later analyses confirmed 1z LPDDR5 dies in products such as the Galaxy Watch7.

Application Domains and Market Impact

Application Segment	Primary Products	Key Benefits Delivered by 1z	Notable Deployments / Timing
Premium Smartphones	12/16 Gb LPDDR5	Higher capacity, thinner packages, higher speed, better power efficiency	Galaxy S21 series (2021); other Android flagships
Servers & Enterprise	8 Gb DDR4 modules	Higher density, improved productivity, energy efficiency	Next-gen servers and high-end PCs (2020 onward)
Graphics / Gaming / AI	GDDR6	High bandwidth, density gains	Graphics cards and accelerators
Automotive	Extended-temp LPDDR / DDR	Reliability across wide temperature ranges	Infotainment and ADAS systems
Wearables / Compact Devices	LPDDR5 in multi-die packages	Ultra-thin form factors, low power	Smartwatches and similar

The 1z process arrived at a pivotal moment: the early commercialization of 5G smartphones and the rising demand for on-device AI features. Higher memory capacity and bandwidth directly supported multi-camera systems, high-resolution gaming, real-time image processing, and early machine-learning workloads on mobile devices. In servers, the productivity gains helped address cost and density pressures in data centers.

Strategic Significance

By delivering the industry’s first high-volume 16 Gb LPDDR5 on an advanced node with EUV assistance, Samsung strengthened its leadership in the premium mobile memory segment. The same process foundation supported a broader portfolio that extended into servers, graphics, and automotive markets. Subsequent nodes (1a and beyond) built directly on the density, power, and packaging advances first commercialized at 1z.

In short, Samsung’s 1z DRAM products were not limited to a single category. They spanned mobile, computing, graphics, and specialized applications, with the most visible commercial impact occurring in flagship smartphones of 2020–2022 and the server market that followed.