Tag: semiconductor

2nm Semiconductor Fabrication: Technical Hurdles in TSMC N2, Samsung SF2, and Intel 18A

“2nm” is a marketing and generational label rather than a literal measurement of any single feature size. It denotes the process generation following 3nm, defined primarily by contacted gate pitch around 45 nm and tightest metal pitch around 20 nm according to industry roadmaps. The real advances lie in transistor architecture, lithography, materials, and power-delivery… Read More 2nm Semiconductor Fabrication: Technical Hurdles in TSMC N2, Samsung SF2, and Intel 18A

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Samsung’s 3nm Process: MBCFET Gate-All-Around Transistors – Architecture, Variants, and Key Advantages Over FinFET

Samsung’s 3nm process technology represents a major milestone in advanced semiconductor manufacturing, as it introduced Gate-All-Around (GAA) transistor architecture to high-volume production ahead of competitors in some respects. Samsung Foundry pioneered this shift from the traditional FinFET design used in earlier nodes (and still used by TSMC at their initial 3nm node). Introduction and Key… Read More Samsung’s 3nm Process: MBCFET Gate-All-Around Transistors – Architecture, Variants, and Key Advantages Over FinFET

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TSMC N3 Family (3nm-class process technologies) Variants Explained: N3B, N3E, N3P, N3X – Architecture, Innovations, and Trade-Offs

TSMC’s N3 family refers to its suite of 3nm-class process technologies, representing the company’s advanced logic nodes based on FinFET transistors. These are the most sophisticated FinFET-based processes before TSMC transitions to nanosheet (gate-all-around) transistors starting with its 2nm (N2) family. TSMC first achieved high-volume production with its baseline N3 (also called N3B in some… Read More TSMC N3 Family (3nm-class process technologies) Variants Explained: N3B, N3E, N3P, N3X – Architecture, Innovations, and Trade-Offs

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TSMC’s N5 5nm Process: Detailed Technical Breakdown, Transistor Scaling, and Evolution to N4 Variants

TSMC’s N5 (commonly referred to as 5nm FinFET or simply “5nm”) is one of the most significant and successful advanced logic process technologies in semiconductor history. It represents TSMC’s full-node advancement beyond the 7nm family (N7, N7+, N6) and became the industry’s first 5nm-class process to reach high-volume production in 2020. As of March 2026,… Read More TSMC’s N5 5nm Process: Detailed Technical Breakdown, Transistor Scaling, and Evolution to N4 Variants

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